Research And Implementation Of A Low-Pass ∑△ Digital To Analog Converter For High-Precision Capacitive Micromechenical Accelerometer Application

Micromechanical accelerometers have been widely used in aerospace,position and navigation,automotive electronics and industrial control because of their small size,light weight,low power consumption,low cost,high reliability and ease of integration.The high-precision capacitive micromechanical acceleration system integrates a sensitive mass,a fixed electrode,and a detection circuit on a single chip to form a system-on-chip(SoC),which further compresses the volume,saves costs,and reduces the effect of parasitic capacitance on the system.within addition to good repeatability,high resolution,low noise,low temperature drift coefficient,low power consumption,and simple structure,the high-precision capacitive accelerometer SoC is a widely studied micromechanical accelerometer.In a high precision capacitive micromechanical accelerometer SoC,a 400 Hz low-frequency acceleration signal needs to be modulated onto a high-precision intermediate frequency sinusoidal carrier(100 KHz-200 KHz)provided by the DAC to reduce noise and offset.The ∑△ DAC utilizes oversampling and noise-shaping technology for high resolution without high-precision components.However,the bandwidth of traditional low-pass ∑△ DACs is only 20 KHz and cannot meet the application requirements.There are no such band pass DACs on the market.By comparison,the low-pass ∑△ DAC with 200 KHz bandwidth indicatates the advantages of simpler structure,smaller chip area,and easier implementation than the 100 KHz～00 KHz band-pass ∑△ DAC.Therefore,this study adopts the low-pass∑△DAC scheme to achieve the system requirements.The main work of the dissertation is divided into two parts,1.In this dissertation,a low-pass ∑△ DAC with a 200 KHz bandwidth is designed and implemented on a SMIC 0.18μm 1P6M mixed-signal CMOS process.The core area is 2.6 mm2.Measured results show that the SNDR is no less than 74 dB in the 200 KHz bandwidth range,and the maximum can reach 78 dB with a dynamic range of 83 dB.Under a 1.8V/3.3V supply voltage,the power consumption with and without a buffer are 40.3 mW and 27 mW,respectively.In comparision with other published low-pass ∑△ DAC studies with similar bandwidths to test results,the FOM of the design in the present work is 152 dB,which is above the average(135 dB).2.The first version of the design was optimized to reduce the power consumption and signal thermal noise of the ∑△ DAC.In comparison with the first version,the post simulation results indicate that the second version of SNDR is improved by 3.7dB and FOM is increased by 4.7 dB.The power consumption with a buffer and without a buffer are reduced by 34.7%and 13.3%,respectively.The core area is reduced by 23%to 2 mm2.The dissertation’s innovations include,1.A new type of ∑△ modulator with high-pass dither is proposed.It not only can significantly reduce the harmonic spurs,but also reduce the noise in the signal band.In comparison with the traditional ∑△ modulator with dither,simulation results indicate that the SNDR is increased by 6 dB.2.Despite numerous studies on the behavioral models of high-speed current-steering DAC and SC delta-sigma modulator for analog to digital converter,no complete model has ever been reported for the design of the switched capacitor∑△DAC.A low-pass switched capacitor ∑△ DAC system-level model with 200 KHz bandwidth is established.This model can guide the design of circuits.3.This dissertation proposes a low-voltage micro-power class-C inverter which simutaneously achieve high gain and wide output voltage swing,and acts as an amplifier.In comparison with the traditional gain boost class-C inverter,the proposed inverter in this study improves the DC gain and output swing by 37.3%and 21.7%under the same power consumption and load conditions,respectively.