Design Of SAR-ADC Used For CZT Detector Imaging System

Cadmium Zinc Telluride(CZT)detector is considered as one of the most promising next generation semiconductor radiation detectors.The imaging systems based on the CZT detector have a wide range of applications,such as space exploration,biomedical imaging,radioactivity detection,safety inspection,and so on.The front-end readout system is the key device of the CZT detector system,the function of which is to amplify,shape and digitize the weak electrical signals generated by the CZT detector.The analog to digital converter(ADC)is an important part in the front-end readout circuit,which is required to have the features of high resolution,high sampling rate,small area,less power dissipation and radiation tolerance.In this thesis,the SAR-ADC(Successive Approximation Register-ADC)aimed to use in the CZT detector imaging systems is designed and implemented,the main contributions and innovations are summarized as follows.1 Main research works(1)Research and design of a capacitor-resister hybrid SAR-ADC chipAimed to use in the CZT detector system for portable?-ray spectrometer,a 12-bit 1 MS/s capacitor-resister hybrid SAR-ADC chip has been designed and implemented.This SAR-ADC is with simple circuit structure and is easily implemented.The DAC is composed of 6-bit C-DAC and 6-bit R-DAC,in which a good tradeoff between the conversion precision and the power dissipation is achieved.In addition,the 6-bit C-DAC is realized by unit capacitor array so as to improve the linearity of the SAR-ADC.The measurement results of the chip indicate that,no missing code exists,and the ENOB can reach up to 10.94-bit with power dissipation of 10 mW.The active area of chip is 1.274 mm~2.(2)Research and design of a unit bridge capacitor structure SAR-ADC chipAimed to use in the CZT detector system for PET biomedical imaging,a 12-bit 1 MS/s unit bridge capacitor structure SAR-ADC chip has been designed and implemented.This SAR-ADC has the features of low power and small die area.Compared with the traditional fractional bridge capacitor C-DAC,the adoption of unit bridge capacitor can improve the matching precision of bridge capacitor.Besides,in order to eliminate the phenomenon of periodic missing codes,the code-randomized calibration technique is proposed for this SAR-ADC.The measurement results of chip indicate that,there are no missing codes after the calibration,and the ENOB can reach up to 11.00-bit with power dissipation of 5 mW.The active area of chip is only 0.943 mm~2.(3)Research and design of a sub-radix-2 capacitor structure SAR-ADC chipAimed to use in the CZT detector system for the space exploration of X/?-ray,a 12-bit1MS/s new ramp digital bit-by-bit calibration sub-radix-2 capacitor structure SAR-ADC chip has been designed and implemented.This SAR-ADC has the features of low power,small die area and radiation tolerance,which is suitable for multi-channel integration.In order to reduce the influence of capacitors mismatch on the conversion precision of SAR-ADC,a ramp digital bit-by-bit calibration algorithm is proposed.The measurement results of chip indicate that,there are no missing codes after the calibration,and the ENOB can reach up to 10.88-bit with power dissipation of 3 mW.The active area of chip is only 0.687 mm~2.The above three SAR-ADC chips are implemented using TSMC 0.35?m CMOS commercial process.(4)The radiation-hardened design in SAR-ADC chipConsidering the SAR-ADC chip developed in this thesis will be used in the space exploration of X/?-ray,the radiation-hardened design is completed in both the circuit-level and layout-level to increase the radiation-hardened ability of it.To eliminate the effects of threshold-voltage shift in CMOS transistors caused by the total ionizing dose effects(TID),the self-cancellation technique of offset voltage is adopted in the comparator design.To eliminate the effects of single-event upset(SEU),the resistance-delay circuit is added in the latch of comparator,and the dual interlocked storage cell(DICE)is used in the shift registers.To eliminate the effects of single-event latch-up(SEL),two radiation-hardened design technologies are adopted in the layout design of the digital standard cells,one is adding the P+and N+guard rings in NMOS and PMOS transistors,the other is enlarging the distance between the PMOS and NMOS transistors.2 Main innovations proposed(1)A self-cancellation technique of offset voltage for high-speed comparator.The offset voltage of comparator influences the conversion precision of ADC seriously.For the traditional offset voltage cancellation technique,since the offset storage capacitors are cascaded on the signal pathway,thus the bandwidth and the response speed of comparator is reduced.A self-cancellation technique of offset voltage in high-speed comparator is proposed in this thesis,in which the offset storage capacitors are removed to the two ends of output loads,and therefore no any capacitor is introduced on the signal pathway.As a result,adding offset storage capacitors do not influence the bandwidth and response speed of the comparator.(2)A code-randomized calibration algorithm to eliminate the periodic missing code phenomenon.Due to the influences of parasitic capacitors,the periodic missing code phenomenon occurs often in the unit bridge capacitor structure SAR-ADC,which degrades the conversion precision of SAR-ADC.In this thesis,a code-randomized calibration algorithm is proposed to eliminate the periodic missing code phenomenon by means of compensating the missing code with the probability of 1/2 by adiacent codes.The proposed calibration algorithm which can eliminate the periodic missing code is simple and can be easily realized.(3)A ramp digital bit-by-bit calibration algorithm.In the traditional calibration algorithm of sub-radix-2 capacitors structure SAR-ADC,the nonconvergence situation may occur,since the weights of all-bits of SAR-ADC are calibrated simultaneously.Thus,the tradeoff between the calibration precision and calibration time is required.In order to overcome above issue,a ramp digital bit-by-bit calibration algorithm is proposed in this thesis.In the calibration stage,a linearly increasing ramp signal is used as the input signal of SAR-ADC,and the output digital codes of SAR-ADC are calibrated bit-by-bit from lower weight bits to higher weight bits,in which the calibrated lower weight bits are utilized for the higher weight bits calibrations.Therefore,the proposed calibration algorithm is simpler,more stable,and faster than the traditional approaches.In this thesis,for the different application fields of CZT detector system,three kinds of SAR-ADC chips were developed successfully based on the innovative technologies proposed,which are with the features of high-precision,radiation tolerance and multi-channel integration.And the achievements obtained in this study have important theoretical significance and pratical values for developing the front-end redout system of the radiation-detectors.