Research On New Structure Of Naonoscale MOSFET Based On Electric Field Modulation

With the continuous development of integrated circuits,as the important component,Metal Oxide Semiconductor Field Effect Transistor（MOSFET）has entered the sub-20 nm regime.The miniaturization process of transistors is facing extremely complex physical and fabrication problems.When the device is scaling into deep nanometer regime,the short channel effect is particularly prominent,seriously affecting the performance and application of the device.Therefore,in order to make the feature size of the transistor can be reduced with the guide of Moore’s Law,research of nanoscale MOSFET to meet the next generation performance requirements is particularly important.MOSFET belongs to the electric field control type of electronic device,the electric field inside the device controls the carrier transport.In this paper,the new structures of high-performance nanoscale MOSFET are mainly investigated.As the MOSFET dimensions scaling down,the lost gate control of the channel is an important issue that should be addressed while providing immunity against short-channel effects.Under the guidance of the theory of three kinds of electric field modulation（gate engineering,channel engineering and spacer engineering）,the effective channel length of the device in the ON-and OFF-state is further controlled,which helps to improve the gate control capability and inhibit the short-channel effects.As a result,the drive current is enhanced and its leakage current is reduced.Several novel nanoscale MOSFET structures with high ON/OFF current ratio are obtained,which provide theoretical guidance for the further miniaturization process of nanometer devices in the future.First of all,the electric field distribution model and current model of nanoscale MOSFET based on Poisson equations and boundary conditions with respect to gate engineering approach are studied.Based on the theoretical model,a new type of DMCG-DGJLT device is studied on the basis of dual gate junctionless transistor（DGJLT）.By using a metal electrode with a higher work function in the middle of the gate,the metal electrode with lower work function is used on both sides to adjust the effective channel length in the ON-and OFF-state.The increment of I_ON and the reduction of I_OFF are achieved.In addition,a higher ON/OFF current ratio and a faster switching speed are obtained.And the gate near the drain region acts as a screen gate,which significantly suppresses the short-channel effects,and provides a certain design idea for the scaling.Secondly,the electric field distribution model and the threshold voltage model of nanoscale MOSFET based on Poisson equations and boundary conditions with respect to channel engineering approach are studied.Due to the low driving current and high sensitivity of the JLT device,a new GC-DGFET structure is investigated under the guidance of the channel engineering theory.Based on the charge plasma concept,the peak electric field near the drain end is further reduced,and an additional peak electric field is generated by introducing the doping gradient in the channel region.Thus,the short-channel effects are suppressed and the driving current is increased.It is worth mentioning that electrostatic doping is achieved in GC-DGFET,which improves the sensitivity and single event effects,and further expands the application of the device.At last,on the basis of the GC-DGFET structure,spacers with high dielectric constant（high-κ）material are introduced.Among them,the pure high-κspacer structure has a single spacer material,whereas,the dual-κspacer architecture can be divided into SymD-κ,AsymD-κS and AsymD-κD GC-DGFET,according to the symmetry of the spacers and the location of the high-κmaterial.Based on spacer engineering approach,the direction of the electric field through spacers is modified in the ON-and OFF-states.This implies that the gate potential elevated the source-side potential and lowered the drain-side potential via spacers,resulting in an increased effective channel length to reduce the OFF current.However,the vertical electric field direction is reversed in the drain extension region in the ON-state.This means that the gate potential elevates the source-side potential via spacers to reduce the electron barrier height near the source,resulting in an increased driving current ION.Therefore,the ON/OFF current ratio and switching speed is further improved.The dual-κstructures exhibit larger fringe capacitances,but both the SymD-κand AsymD-κS architectures show better intrinsic delay performances.Overall,the SymD-κand AsymD-κS architectures exhibit excellent device performance that would anticipate better logic digital circuit performance.