Research Of Digital Signal Processing Electronics In The Bunch-by-bunch Transverse Feedback System Of SSRF

Shanghai Synchrotron Radiation Facility(SSRF)is one of the third generation of synchrotron radiation sources,which is built in China.Its main performance ranks first class worldwide.It consists of a 150 MeV electronic linear accelerator,a 3.5 GeV booster,a 3.5GeV electronic storage ring,beamlines and experimental stations.With the continuous increase of the beam current in the electron storage ring in SSRF,the transverse instability of the electron bunches becomes more and more serious,which becomes an important factor to control the beam quality.In order to suppress beam instabilities,a transverse feedback system is indispensable.Aiming at such requirement in SSRF,this paper focuses on the design of digital signal processing electronics,which is the key part in the whole feedback system.In the feedback system,high precision samples of each bunch signal with a repetition frequency of 499.654 MHz is required,and base on this information feedback information is calculated real time based on digital signal processing,and then converted to analog signals back by high-speed DAC,which is finally used to tune the corresponding bunch through kickers.To address such issues,efforts were devoted to research of high-speed high-resolution ADC,DAC,and real-time algorithms implemented in FPGA devices.This algorithm can even manipulate any single bunch according to the demands in machine research.One important task in the electronics is precise time synchronization.First,the sampling clock phase of ADC needs to be finely adjusted to make it samples at the bunch waveform nearby its peak.Second,the clock of the DAC also needs to be delayed to a certain phase,which make the feedback takes effect at the right time point when the beam bunch pass through the kickers.In traditional methods,cables with different lengths are employed to achieve signal delay,and choosing a suitable cable became quite an inconvenient task.In this dissertation,a signal delay scheme is proposed based on multiple levels of coarse time and fine time adjustment,which consists of FPGA logic,multiple stages of PLLs and external delay line chips.And fine delay with a step size of 10 ps and a range up to 2.8?s is achieved.Meanwhile,the above components can be controlled digitally by FPGA,rendering a good system flexibility.Tests were conducted to evaluate the system performance,and the results indicate that the main performance meets the requirements,in which the suppression ratio of the operating points in the horizontal and the vertical directions is better than 30 dB.Initial commissioning tests with the beam in SSRF was also conducted,and the results concord well with the expected.The first chapter includes the review of the synchrotron radiation accelerator and the introduction of the SSRF.Then the necessity of transverse feedback system is introduced.In the second chapter,the transverse instability is presented and several transverse feedback systems are reviewed.The causes of the beam instability are analyzed,and the transverse motion equation of the electron beam and the measurement method of the transverse oscillation operating point are given.The transverse oscillation mode and the damping principle of the spectrum and transverse feedback system are discussed.And then the beam feedback systems are categorized with some typical examples.The third chapter elaborates the electronic design scheme of digital signal processing for transverse feedback.Firstly,the overall structure of the system is introduced,and then the RF signal conditioning scheme is discussed and simulated.According to the characteristics of the input signal and the application requirement,scheme of the signal processing electronics is then determined.Schemes of three parts are presented in details,including the construction of clock generation circuits and the desigin of digital filter.Chapter 4 and Chapter 5 includes the information regarding the hardware implement.Chapter 4 presents the design of the hardware circuits,including choice of key chips in the electronics,optimization of the front-end circuits of ADC,clock circuits,as well as the whole PCB layout consideration to guarantee the SI(Signal integrity).Chapter 5 describes the FPGA hardware logic algorithm implementation and simulation,as well as the data cache and transmission interface design.To evaluate the system performance,the sixth chapter presents the test results of the electronics.These results are beyond the application requirements.Initial commissioning tests were also conducted,with the results indicating that effective suppression of the transverse oscillation is successfully achieved.Chapter 7 includes a summary of the work and the outlook for the future work.