| It has become increasingly difficult to improve the performance of integrated circuits by reducing the feature size of transistors according to Moore's Law.Three-dimensional integrated circuit(3D IC),as an important research program and application direction of More than Moore,will fundamentally change the development trend of integrated circuits.The gap between stacked chips and the pitch between bumps have been scaled down significantly under the trend of miniaturization of IC devices,such that the traditional underfilling and micro interconnect reliability become the critical issues for wafer-level 3D IC integration.Wafer-level hybrid bonding technique that allows simultaneous bonding of metal part and dielectric part is an enabling technology to not only address the challenges of underfilling but also significantly enhance the reliability of micro interconnects.At present,how to design and manufacture hybrid bonding-based 3D IC integrated devices with high yield,excellent reliability and easy for industrialization has become a key challenge facing the industry.In this study,an 8-inch wafer-level 3D IC stacking technique based on Cu/solder micro bumps and adhesive hybrid bonding technique and via-last through silicon via(TSV)was studied.The adhesive was lithographed to expose the micro bumps,which is comparatively simple and efficient.By analyzing the bonding mechanism and optimizing the bonding process and parameters,the wafer-level hybrid bonding with good performance and reliability has been achieved.This method eliminates the demand for thin wafer handling and chemical mechanical polishing surface pre-treatment technique,which makes it easier for industrialization.The main results are summarized as follows:1.The wafer-level adhesive bonding properties of two kinds of typical adhesive materials,i.e.,polyimide(PI)and dry film(DF),were firstly studied.The microstructure of the bonding interface,mechanical properties and reliability of the stacked chips based on adhesive bonding were analyzed.A seamless adhesive bonding interface can be obtained using either PI or DF adhesive.However,the stacked chips using DF adhesive own higher bonding strength and better reliability.Further,two kinds of hybrid bonding structures,i.e.,Cu/SnAg micro bump and PI adhesive&Cu/SnAg micro bump and DF adhesive,were studied.The reliability of the hybrid bonded wafers during the sawing process,the microstructure of hybrid bonding interface and the mechanical properties of the hybrid bonded chips were characterized.Although both the hybrid bonding schemes can achieve seamless hybrid bonding interface,the stacked wafers using PI adhesive as adhesive cannot sustain the sawing process.The saw test and the shear test indicate that the hybrid bonding strength using DF adhesive is much more robust.Thus,dry film is more suitable for Cu/SnAg micro bump and adhesive low-temperature hybrid bonding structure.2.The hybrid bonding structure using Cu/SnAg micro bumps with equal diameter and DF adhesive and the bonding mechanism were studied.For this hybrid bonding structure,the upper and lower micro bumps are higher than the DF adhesive.Firstly,the effects of soft-bake pretreatment of DF adhesive and two kinds of bonding profiles(conventional bonding profile and optimized step applying force bonding profile)on misalignment between the upper and lower wafers during the hybrid bonding process were investigated.X-ray technique was used to detect the misalignment.A misalignment value of only about 5 ?m is obtained using soft-baked DF adhesive and optimized step applying force bonding profile.By measuring the misalignment values at different locations of the 8-inch bonded wafer pair,we conclude that the mechanism for misalignment during the hybrid bonding process is slip.Secondly,the effects of total height difference between the Cu/SnAg micro bump part and the DF adhesive part and bonding force on hybrid bonding performance were investigated.C-mode scanning acoustic microscope(C-SAM)was used to detect the locations of the unbonded areas.The results show that the seam can easily form at the DF adhesive bonding interface with a large total height difference;while an optimal bonding result is obtained with a total height difference of 2 ?m and an enhanced bonding force of 3 KN.The unbonded areas only appear at the center of the bonded wafer pair.The statistical analysis of the micro bump height shows that the unevenness of the micro bump height results in the unbonded region.3.A hybrid bonding structure based on insert micro bumps and DF adhesive was developed.Firstly,the effects of two kinds of hybrid bonding methods,i.e.,adhesive-first bonding and micro bump-first bonding,on post-bonding misalignment and microstructure of bonding interface were studied.It is found that the misalignment values of the two kinds of hybrid bonding methods are both lower than the design misalignment tolerance(9 ?m),and the micro bump-first hybrid bonding method is more liable to obtain a seamless hybrid bonding interface.Then backside grinding was performed on the hybrid bonded wafers using micro bump-first bonding method followed by fabricating via-last TSVs with a diameter of 40?m and a depth of 93 ?m.The wafer-level electrical test shows that the entire stacked wafer pair has a well electrical connectivity,indicating that the micro interconnects and TSVs are successfully integrated.The shear test shows an average shear strength of 28.7 MPa.After hybrid bonding,Cu/Ni-P/P-rich Ni/Ni3Sn4 IMC+sodler/Ni/Cu micro interconnects form by interfacial reaction between the micro bumps.The reason why the Ni3Sn4 IMC layer on the Ni-P side is significantly thinner than that on Ni-side was explained.Reliability of the hybrid bonded chips were characterized.The microstructure evolution of the IMCs at the micro bump bonding interfaces with reliability test duration was revealed as well. |
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