Modeling And Synthesis For Approximate Computing

Reducing power consumption is becoming increasingly significant in today’s very large-scale integration(VLSI)design.Meanwhile,many applications that exhibit an inherent tolerance to errors in computation,such as multimedia,signal processing,and data mining,become more widely used in recent years with the prevalence of mobile computing and embedded systems.Given this context,an unconventional design paradigm — approximate computing,is proposed to design energy-efficient digital systems targeting at those error-tolerant applications.Approximate computing employs active design methodologies to exploit the fact that many applications can tolerate some quality loss in computation.Its effectiveness has been demonstrated at different levels from algorithms,architectures,to logic and transistors.However,as an emerging design paradigm,approximate computing is still in its initial stage of development.To move approximate computing to the mainstream requires many issues to be solved,one of which is the modeling and analysis of accuracy.Solving this problem can help users decide whether an approximate design meets their requirement or choose the most suitable approximate implementation from multiple available designs for a given application.For error tolerant applications which are usually computationally intensive,the addition operation is the most vital component since it is the foundation of other more complex operations such as multiplication and division.Due to this reason,many designs of approximate adders have been proposed.To get the comparative performances of these approximate adders,a systematic,accurate,and efficient method is indispensable.Besides the analysis of approximate circuits,another major task in facilitating the adoption of approximate computing is the design of approximate circuits.The idea of approximate circuit design is to deliberately introduce a reasonable amount of errors into a circuit with the purpose of trading off accuracy for improvement in the circuit area,delay and/or power consumption.Lots of pioneering research efforts in designing approximate circuits focus on the manual design for basic arithmetic units,such as adders and multipliers.Later,approximate logic synthesis(ALS),which automatically synthesizes an approximate circuit for a specified Boolean function under the given error constraints,was proposed as a more promising approach,since it allows larger design space exploration and can be applied to general-purpose functions.However,research on ALS is still in its early stage and more efforts need to be made to push the development of ALS.To address the problems mentioned above,this dissertation focuses on the error modeling of a prevalent class of approximate adders and the approximate logic synthesis for two mainstream integrated circuits(ICs).Specifically,three research works will be presented in this dissertation.In the first work,we propose an efficient method to obtain the error statistics of a class of approximate adders with good performance,which is called block-based approximate adder.Compared to the state-of-the-art method targeting at the same class of approximate adders,our method has great advantage in CPU runtimeand is much more scalable,which is essential for practical use in real applications.In the second work,we are dedicated to ALS for Application-Specific Integrated Circuits(ASICs)under the constraints of error rate and error magnitude.In the third work,we target at ALS for Field-Programmable Gate Arrays(FPGAs)with single error rate constraint.Since FPGAs have different structures and are composed of different basic functional units from ASICs,we propose different approximation methods for the synthesis of approximate ASIC-type and FPGA-type circuits,respectively.Experimental results for the proposed algorithms in these two works show that our synthesis approaches could produce approximate circuits with lower area cost compared to the state-of-the-art methods while consuming less or comparable CPU runtime.