Software And Hardware Characteristics-Aware Adaptive Power Management:Models And Optimizations

Energy consumption has become a major factor in the design and implementation of mod-ern computer systems.In many systems,both processor(or CPU)and main memory(or DRAM)are most critical components for the performance and energy consumption.Reducing the energy consumption of computer systems is critical for their scalability,sustainability and affordability.For these reasons,this thesis investigates whether and how we can leverage CPU and DRAM power management techniques to reduce the energy consumption of computer systems.Current power management mechanisms of CPU and DRAM lack the adaptivity of differ-ent system architectures and different workloads as well as different optimization goals.They lose the opportunities in exploiting the most energy-effective power management scheme for different workloads and different system architectures.Due to the inherent power management mechanisms of CPU and DRAM,we find there are several obstacles in the effectiveness of re-ducing the energy consumption of computer systems.First,modern DRAM architectures allow a number of low-power states on individual memory ranks for advanced power management.Many previous studies have taken advantage of demotions on low-power states for energy sav-ing.However,most of the demotion schemes are statically performed on a limited number of pre-selected low-power states,and are suboptimal for different workloads and memory ar-chitectures.Even worse,the idle periods are often too short for effective power state transi-tions,especially for memory intensive applications.Wrong decisions on power state transition incur significant energy and delay penalties.Second,dynamic frequency scaling(DFS)and DRAM low-power states(Demotion)are two main-stream techniques for DRAM power man-agement.DFS reduces the operation frequency of memory channels and DRAM devices when the memory bandwidth is under-utilized,whereas demotion transits individual memory ranks to low-power states during long idle periods.Despite that there have been fruitful research work for DFS and demotion separately,little attention has been paid to the synergy between these two techniques.Third,dynamic power management schemes can significantly reduce the to-tal energy consumption of processors by leveraging CPU sleep states.Prior work has focused on single-thread applications with a stable workload.Recently,multi-thread latency-sensitive services,such as intelligent personal assistant service,Microsoft Bing,and compute-intensive financial service,are widely used in current datacenters.However,the variability of user queries in these service makes existing schemes ineffective,leading to either quality of service violations or higher energy consumption.For these reasons,this thesis proposes software and hardware characteristics-aware power management techniques of CPU and DRAM to reduce the energy consumption of computer sys-tems effectively,adapting to different workloads and different system architectures as well as different optimization goals.First,we propose a novel memory system design named RAMZzz with rank-aware energy saving optimizations including dynamic page migrations and adaptive demotions.Specifically,we group the pages with similar access locality into the same rank with dynamic page migrations.Ranks have their hotness:hot ranks are kept busy for high utilization and cold ranks can have more lengthy idle periods for power state transitions.We further de-velop adaptive state demotions by considering all low-power states for each rank and a prediction model to estimate the power-down timeout among states.RAMZzz is able to optimize for differ-ent goals such as energy saving and energy-delay~2(ED~2).We evaluate RAMZzz in comparison with representative demotion-based power saving policies and an ideal oracle approach.Our experiments with the optimization goal of ED~2(for a maximum acceptable performance degra-dation of 4 percent)on three different DRAM architectures show that with both page migrations and adaptive demotions,RAMZzz achieves an average ED~2improvement of 23–54 percent over other demotion-based approaches.Next,to bridge the gap between DFS and demotion,we conduct a comprehensive study on the synergy between DFS and demotion,and propose a new memory system design named Hy-brid.In particular,we leverage queuing theory to develop analytical models for the energy con-sumption and performance of DRAM systems with DFS and demotion.These models provide valuable insights into the synergy between DFS and demotion.We find that there is a complex interplay between DFS and demotion in optimizing memory energy consumption.We further attempt to minimize the energy consumption by considering both DFS and demotion while keeping a pre-defined performance penalty budget.To reduce the optimization complexity,we develop simple yet effective heuristics to search near-optimum DFS-demotion configurations.We evaluate our approach in comparison with the state-of-the-art approach using demotion or DFS techniques only as well as the static combination of DFS and demotion.The experimen-tal results show that our approach achieves an average energy consumption reduction of 11–70percent over the demotion-only approach,20–67 percent over the DFS-only approach,22–54percent over the static combination of DFS and demotion.Finally,in order to minimize the energy consumption while guaranteeing the quality of service of multi-thread latency-sensitive applications,we propose Electro,a machine learning enhanced dynamic CPU power management system.Specifically,Electro consists of a query du-ration predictor and a query consolidating engine.The duration predictor can precisely predict the duration of each user query in different scenarios based on the pre-trained duration models.At runtime,according to the predicted duration,the query consolidating engine consolidates user queries accordingly to maximize the duration of the CPU idle states while guaranteeing the quality of service.The longer each idle state is,the deeper low-power sleep states can the CPU enter.Our evaluation results on the latest Intel Xeon V4 CPU show that Electro reduces the en-ergy consumption of CPU by 82 percent on average compared with the default OS scheduling and by 14 percent on average compared with the state-of-the-art technique,while achieving the95 percent-ile latency target for latency-sensitive applications.