Research And Design On Low-voltage And Low-power SAR ADC

Analog-to-digital converter(ADC)is an indispensable part of most electronic systems,and the performance characters of ADC restrict the performance of the whole electronic system.Successive approximation register(SAR)ADC gains advantages in low power consumption among other kinds of ADCs,because of its simple system architecture and no need for power hungry modules.In addition,with the development of advanced CMOS technology,the supply voltage of integrated circuits are getting down,and the transconductance of CMOS transistor is getting lower,which is a serious challenge for analog design.Since SAR ADC is highly digitalized,it is suitable for the advanced CMOS technology,which makes SAR ADC a popular research area.Portable devices are commonly powered by butteries and energy harvesting blocks,and the duration of the devices can seriously affect the user experience.Hence it it necessary to design low-voltage and low-power SAR ADC.SAR ADC consists of four building blocks,i.e.sampling circuit,capacitor array,comparator and control logic.The problem of how the performance charater of those building blocks affect the performance of the whole SAR ADC system is analyzed from one block to another.The building blocks which restrict the performance of low-voltage and low-power SAR ADC are promoted.Moreover,the analysis and promotion are demonstrated by model-level simulation,circuit-level simulation and chip testing.Sampling circuit is the first block that the input signal is guided into the ADC system.The speed and linearity performance of sampling circuit determine the upper limit of the whole ADC.The conventional clock boosting circuit is promoted to level-shifted boosting circuit,and two conventional clock boosting circuit and a level-shifted boosting circuit are cascaded together to gengerate a sampling signal with enough overdrive voltage and sharpe enough falling edge under 350 mV supply voltage,which can support the sampling for 8 bit and 12 MS/s.The proposed speedup comparator can enhance the speed of comparator,and,at the same time,remain the noise performance.The power/ground latch register can greatly reduce the propogation delay to not more than two-gates-delay.A SAR ADC is designed to achieve 350 mV 12MS/s with those techiniques and the effective number of bits(ENOB)and figure-of-merit(FoM)are 7.82 bit and 2.47 fJ/conv.-step,respectively.Newly deisgned architecture of delta-measurement SAR ADC has two capacitor arrays,and the main DAC and auxiliary DAC are connected by the bridge capacitors.The delta voltage of the current sampled voltage and the last one can be achieved by switching the auxiliary DAC.Adiitionally,when the input signal changes slowly,the delta-measurement SAR ADC can achieve the delta voltage by only switching a few number of small weighted capacitors.Adaptive threshold-first switching scheme is proposed in this work,which is developed from least significant bit(LSB)-first SA scheme and Vcm based switching scheme.The adaptive threshold-first switching scheme can get the proper threshold according to the changing rate of the input signal to achieve the least number of successive approximation(SA)cycles and the lowest switching energy of the DAC.The system-level model simulation shows the delta-measurement SAR ADC with adaptive threshold switching scheme can greatly decrease the number of SA cycles,and even when the input signal changes violently,the number of SA cycles remains around 10.Moreover,if the input signal is a slowly changing signal,the proposed SAR ADC can save more than 90%switching energy compared to the most effective LSB-first SA scheme.Voltage controlled oscillator(VCO)-based comparator generates the decition bit and the number of oscillation cost to get the decition bit,at the same time.The number of oscillation cycles has some relationship with the voltage range of the input signal,which has not been discovered by the former designers.VCO-based comparator and bypass window technique are combined together in this work,and the number of oscillation cycles is used as the trigger signal of bypass window,which can realize smaller power consumption without extra reference and circuit.Adaptive bypass window technique can detect wheather the size of the preset bypass window is too small,and then the size of the preset bypass windows can be enlarged.No special input signal is needed for the calibration and the adaptive bypass window technique is a realtime and background calibration.Since each number of oscillation cycles corresponding to a different bypass window,multiple bypass windows are employed in this work.Analysis and simulation have been carried out to prove that SAR ADC with multiple byass windows are more effective in low power than that with single bypass window.The noise performance and offset of the VCO based comparator and the deadzone of the phase detector are analyzed,and simulations are carried out to verify the analysis.The proposed VCO-based SAR ADC with adaptive bypass window is fabricated in 40 nm CMOS technology,and the implemented SAR ADC with tt,ff and ss process corners is tested under 0.5~1.1 V supply and 0~100 ~oC temperature,which proves the adaptive bypass window technique is robust to PVT variation.The measurement results show the SAR ADC can achieve good FoMs of 2.4~6.85 fJ/conv.-step under 0.5~1.1 V supply.Phase-locked loop(PLL)generates clock signal for ADC,whose performance affects the ADC seriously.The sinusoidal oscillation for unstable PLL is analyzed.If the overshoot problem is ignored,the output of the unstable PLL reaches the goal frequency in a very short time.Phase error cancellation technique can greatly decrease the locking time form PLL.The schematic of the fast-lock PLL is simulated under 0.13μm CMOS technology.The simulation results show the proposed fast-lock PLL can save over 87%settling time compared to the conventional PLL.Additionally,with PVT variation,the proposed PLL can reduce at least 78%settling time over conventional PLL.