| The Interconnects among more than a billion transistors on a single chip are widely recognized as the performance bottlenecks in nanometer scale integrated circuits. Shrinking interconnect dimensions as well as noise and timing budgets have made accurate full-chip interconnect parasitic extraction an indispensable yet (computationally) formidable task, while simultaneously raising concerns about the reliability limits of prevalent Copper interconnects.;This dissertation addresses two important challenges faced by interconnects in nano-scale VLSI technologies - the efficient and accurate modeling of high-frequency (20-100 GHz) electromagnetic phenomena, as well as the material limitations of prevalent Copper interconnects. We first describe an implicit Green's function based method to analytically compute the frequency-dependent impedance of interconnects under the effect of magnetically induced eddy currents inside the large multi-layer Silicon substrate. In lieu of electromagnetic field solvers or numerical codes (which, although computationally expensive, are at present the only way to reliably incorporate these effects), we propose analytical expressions that give errors less than 3% and reduce the computation cost by more than an order of magnitude. Besides outperforming prior works addressing two-dimensional interconnect structures, we successfully generalize our technique to three-dimensional interconnects (including on-chip spiral inductors) over a multi-layer substrate, in ways that are considerably simpler than has been done before.;Secondly, we investigate the limitations of scaled Copper interconnects in meeting the current density requirements in future technologies and explore the possibility of using emerging Single-Walled Carbon Nanotubes (SWCNTs) as an alternative material for VLSI interconnects of the future. This work constitutes some of the first published reports addressing the applicability of carbon nanotubes as VLSI interconnects, showing that SWCNT interconnects can reduce global interconnect delay by up to 40% and also reduce power dissipation in these wires by up to 8x (in comparison with Cu at the 14 nm node). Furthermore, it is shown that SWCNT based vias can not only eliminate many reliability concerns of scaled Cu vias, but can also improve the thermal reliability of the entire interconnect back-end, by lowering the temperature of the hottest interconnects. |
