| Off-axis electron holography has been used to study silicon (Si) heavily-doped N-type and P-type (N+/P) junctions, silicon germanium and silicon (SiGe/Si) heterojunctions, silicon-on-insulator (SOI) structure, and 90-nm metal-oxide-semiconductor field-effect transistors (MOSFETs).; Diffusion of phosphorus around the edges of nitride and oxide diffusion layers grown by low-pressure chemical vapor deposition were studied with an emphasis on the lateral diffusion characteristics. Enhancement under the nitride mask was explained by Si surface oxidation during dopant diffusion process, which involved self-interstitial injection to the underlying Si substrate. Changes in built-in potential across N+/P junctions were measured under various bias conditions.; Mean inner potential (MIP) of strained SiGe layers grown on relaxed Si substrate was experimentally obtained as a function of germanium (Ge) composition. Linear dependence of MIP on Ge composition was shown by holographic data obtained from three different SiGe layers. Negative bias on the SiGe side amplified the built-in potential on the Si substrate side while positive bias decreased the built-in potential.; An SOI structure was used to fabricate pseudo-MOSFET device using two focused ion beam (FIB)-deposited Pt electrodes on the top Si layer. Results showed significant charging in the buried-oxide layer (BOX), causing positive curvature inside. No consistent changes in electrostatic potential in the top Si layer were obtained under various bias conditions due to charging. Carbon coating one side of sample removed the curvature in the BOX layer.; Quantitative analysis of two-dimensional (2D) electrostatic potential distributions in 90-nm Si PMOSFET devices has been carried out. For two MOSFETs with different offset spacer oxides, the separations of extension junctions and source/drain junctions were measured and found to be slightly smaller than the difference in thickness of the offset spacer oxide. The metallurgical gate length was measured to be 52 nm for 0-nm offset spacer FET and 65 nm for 14-nm offset spacer MOSFET. The 0-nm offset spacer MOSFET had a larger overlap (8 nm) between gate and extension regions than that (2 nm) of the 14-nm offset spacer MOSFET. |
