| Aggressive scaling of metal-oxide-semiconductor field effect transistors (MOSFETs) has revealed challenges for their utilization in dense, low-power integrated circuit applications. As the MOSFET is miniaturized, off-state leakage current increases. Additionally, MOSFET switching abruptness is limited to be no steeper than 60mV/decade at room temperature, preventing reduction of operating voltages for low-power applications. To address these challenges, nanoscale electromechanical systems (NEMS) devices have been proposed. NEMS-based switches are expected to provide ideal switching characteristics (i.e., abrupt switching and zero off-state current) and are therefore attractive candidates for dense, low-power applications. In this dissertation, device and process phenomena pertinent to low-power NEMS are presented.;Firstly, adhesion force resulting from W and W/TiO2 contacts in microscale relays is investigated. Adhesion force is identified as a parameter that will ultimately limit the reduction of operational voltage (and hence energy efficiency) in relays. Low adhesion force (∼15nN/micro m2) and a weak dependency on contact force (<6.6x10 -3nN/nN) are observed. Also, adhesion force is found to scale with contact area in contacts as small as 1micro m x 5pm. Finally, TiO2 contact coatings (used to enhance device endurance) are found to increase adhesion force, presenting a trade-off between energy efficiency and device reliability.;Next, scaling flexural electromechanical devices within material strain limits is explored. First, a qualitative model is developed to gain insight. Then, numerical analyses are performed (and verified with 3-D finite clement analyses) to find beam-length scaling limits. Minimization of actuation gap and beam thickness are found to be advantageous for area and voltage scaling. In order to reduce internal beam strain, a pinned-contact configuration is found to be desirable. Target materials for aggressive area and voltage scaling are identified as those with low elastic modulus and high strain limit.;Nanometer-scale gap (nanogap) formation is then investigated in Si/SiO 2 structural/sacrificial systems. New optical and electrical methods for characterizing nanogaps are developed and utilized to study the effect of gap size, etch chemistry and rapid thermal annealing on etch rates. Nanogap etch rates are found to slow markedly in gaps smaller than 50A and as a result of rapid thermal annealing at temperatures >700°C. The formation of nanogaps as small as 40A in height are demonstrated. Finally, nanogaps are incorporated into transistors to develop new applications in sensing, computation and memory. |
