Study of reliability mechanisms and their interaction in nanoscale CMOSFETs

This dissertation is a study of device reliability issues and their interactions in nano-scale bulk and SOI CMOSFETs. As integrated circuits (ICs) become smaller and faster, susceptibility of devices to damage increases due to higher current densities, increased electric fields and lower voltage tolerances. With the technology scaling, not only the reliability problems are increasing but also the interaction between reliability mechanisms. This work focuses on understanding the major reliability concerns electrostatic discharge (ESD), negative bias temperature instability (NBTI) and hot carrier injection (HCI), and their interactions in both bulk and SOI MOSFETs.;In this dissertation, by investigating various aspects of ESD behavior involved in advanced 65nm CMOS technology, it is identified that the power dissipation volume, location of parasitic bipolar transistor (pBJT) formation, and the gain of pBJT plays a competitive role in determining the ESD robustness with technology scaling. From leakages current measurements following ESD stress and device simulations, it is concluded that the thin gate-oxide MOSFETs fail due to both drain-to-source filamentation and oxide breakdown, whereas only drain-to-source filamentation occurs in thick gate-oxide MOSFETs.;The interaction between ESD and NBTI in bulk pMOSFETs is addressed next. Thick oxide devices that are subject to NBTI pre-stressing show increased ESD snapback on-resistance. Similarly, non-destructive ESD pre-stressing is shown to worsen the subsequent NBTI degradation of thin oxide devices.;The dissertation then focuses on the HCI and NBTI studies on bulk pMOSFETs as a function of channel length with various stress bias conditions at both room and high temperatures. The results reveal the increased influence of NBTI like degradation under hot carrier stress (HCS) condition at high temperature.;The dissertation then explores the ESD behavior of SOI n and p channel MOSFETs for various design (channel length and gate-oxide thickness) and layout parameters (gate-silicided and gate-non-silicided). The issues specific to SOI MOSFETs such as floating body and self-heating are studied to assess the ESD robustness of devices under investigation.;Finally, the dissertation presents a comprehensive study on the NBTI and HCI behavior of core logic/high speed (thin-oxide) and Input/Output (thick-oxide) SOI p-channel MOSFETs. The analysis of grounded body 65 nm SOI pMOSFETs show higher NBTI degradation than floating body devices due to the lowering of the oxide field in the floating body devices caused by the gate tunnel current.