Robust device modeling with process variation consideration and dimension reduction techniques

Nowadays the highest device integration affects the design process in several ways. The process variations (PV) significantly impact the circuit performance. As a consequence, a major consideration is determining the production yield relation to the technology based manufacturing variations. The traditional Monte Carlo based sampling analysis became computationally not practical solution due to the extensive parameter set and computationally demanding transistor models. Hence the overall simulation time increases rapidly. Additionally the higher device integration requires dealing with numerous local and global parameters. Clearly all these factors can bottleneck the efforts of achieving fast design cycle, resulting in dramatic computational cost increase along with the decrease of the transistor size.;Statistical analysis can be facilitated by estimating a direct relation of circuit performance factors to the PV parameters. The compact transistor models such as BSIM or PSP use a large number of parameters and equations. However various performance factors can be related to few circuit parameters. For complementary gates we propose new macro model, where all static and dynamic characteristics are related to set of Finite Points. All timing and power related quantities can be predicted by evaluating the model equations. The dynamic characterization relies on charge distribution at each node. The affect of all PV is represented with parameterizing the FP sensitivity to the all variational sources. In overall the new gate model employ same computational structure for different gates and related to traditional BSIM models is in far more simple computational form. This results in more efficient Monte Carlo analysis.;Large scale circuit analysis based on the FP models can be used for estimation of various global performance parameters. These circuit measures such as propagation delay for example is evaluated gradually from the circuit input to desired output. Therefore at each computational step the objective functions such as intermediate delays are related to larger set of parameters including the process variations. Motivated by the limitations the traditional PCA, in order to simplify the overall computational cost, an efficient reduction technique is proposed. Additional information for pruning new dimensions is obtained from measuring the input output correlation where any local performance metrics consist parameters as input and performance measure as output. If this relation is unknown, Sliced Inverse Regression (SIR) technique can be used to determine the Effective Reduction Space (EDR). However if the empiric performance analytic expression is established, the EDR is found by using Principle Hessian Method (PHD). Here the Hessian matrix of the performance function spans additionally the parameter space to the initial reduction ruled by PCA. In theoretical aspect the inverse technique reduces parameters in the sense of their statistical significance.