| As MOSFET gate lengths are scaled below 45nm, fundamental physical limitations are for the first time presenting barriers to further scaling. Among the most important of these barriers is the 'kT/q' limitation which, due to the thermal distribution of carriers, limits the rate at which a MOSFET can be turned on or off with respect to applied gate voltage. This means that as supply voltages are reduced, leakage power is increasing exponentially. At the same time, the number of transistors per chip and the die size of microprocessors have also been increasing with each subsequent technology node. The end result is that source/drain leakage current is quickly becoming the most significant source of power dissipation in modern microprocessors.;This dissertation begins with a review of the MOSFET leakage power problem as well as a systematic study of the possible ways to overcome the 'kT/q' limitation. The subsequent chapters deal with a specific device, the Band-to-Band Tunneling (BTBT) transistor (BTBT-FET), which has the potential to beat the 'kT/q' limit. The physics of BTBT are first reviewed, and then a thorough study of BTBT-FET scaling is presented with both experimental and simulated results. The use of different channel materials and device structures are examined to explore the design space of BTBT-FETs and to gain insight into the practical prospects for these devices to outperform MOSFETs. A novel BTBT-FET structure, the depletion mode BTBT-FET, is examined, and experimental demonstrations are presented. The same doped-body devices used to demonstrate depletion-mode BTBT-FETs are also used to provide an experimental demonstration of the differences between lateral-mode, or source-induced, tunneling, and vertical-mode, or gate-induced, tunneling. Finally, circuit and reliability issues facing BTBT-FETs are presented, and directions for future research are discussed. |
