Radiation hardened high performance microprocessor cache design

As CMOS processes scale down in physical dimension, the scaled circuits become more vulnerable to radiation-induced upset. Soft errors caused by this vulnerability have challenged many designers. Since this is a major problem for microelectronic circuits used in spacecraft, designers have offered a variety of solutions. Radiation-hardening-by-design (RHBD) is a promising approach, where electronic components are designed to work properly in certain radiation environments without special fabrication processes. This work focuses on the cache design for a high performance microprocessor. The design mitigates both single event effects (SEE) and total ionizing dose (TID) effects, using generally available commercial fabrication processes on a commercial foundry 90-nm process.;The cache design is a 16 KB, 4-way set associative, write-through design that uses a no-write allocate policy. Fabricated cache data arrays have been tested to write and read at 1.02 GHz at VDD = 1.3 V. The maximum cache power is 182.2 mW at 1 GHz and VDD = 1.2 V. Annular NMOS transistors, guard ring, interleaved layout, parity protection, dual redundancy, and checking circuits are used in the design to achieve radiation hardness. High speed is accomplished through the extensive use of dynamic circuits and short wiring routes. Gated clocks and optimized wire connections are used to reduce power. Silicon tests demonstrate that the cache design satisfies the function, speed, and power requirements. The SEE and TID hardness have been proved through Co-60 irradiation tests and beam tests at Cyclotron Institute of Texas A&M University.