Digitally calibrated analog-to-digital converters in deep sub-micron CMOS

We present and implement an adaptive digital technique to calibrate pipelined analog-to-digital converters (ADCs). Rather than achieving linearity by adjustment of analog component values, the new approach infers component errors from conversion results and applies digital postprocessing to correct those results. The scheme proposed here draws close analogy to the channel equalization problem commonly encountered in digital communications. We show that, with the help of a slow but accurate ADC, the proposed code-domain adaptive digital filter is sufficient to remove the effects of component errors including capacitor mismatch, signal-dependent finite op-amp gain, op-amp offset, and sampling-switch-induced offset. The algorithm is all digital, fully adaptive, data-driven, and operates in the background. Strong tradeoffs between accuracy and speed of pipelined ADCs are greatly relaxed in this approach with the aid of digital correction techniques. Analog precision problems are translated into the complexity of digital signal-processing circuits, allowing this approach to benefit from CMOS device scaling in contrast to most conventional correction techniques.;To demonstrate the idea, a prototype has been designed and fabricated in 0.13microm with 1.35V power supply. The system mainly consists of a pipelined ADC, a reference ADC, and an adaptive digital filter in FPGA. The measured results show that the SNR improves from 28.1dB before calibration to 59.4dB after calibration at 10OMS/s with a 411kHz. The SFDR improves from 29.8dB to 67.8dB. The total power consumption of the chip is 448mW and the estimated power consumption of the adaptive digital filter is 7mW at 100MHz.