Development of a strained silicon-germanium channel PMOSFET integrable in an existing silicon-germanium HBT technology

In this dissertation, the proposal and development of a strained SiGe-channel PMOSFET, fully integrable in a standard SiGe BiCMOS process is presented. The device uses the n-type polysilicon emitter layer of the bipolar transistor as the gate, and has a p-type SiGe channel, making it a truly buried channel device. The basic device design was systematically optimized by TCAD simulations to get the best compromise between hole confinement in SiGe and channel hole mobility along with maintaining thermodynamic stability. Optimization was done using Ge fraction dependent process and device simulation parameters. A novel, semi-analytical approach to model the effect of Ge fraction on hole current was used. The impacts of Si cap layer thickness, SiGe thickness, channel doping and Ge fraction were investigated. The optimized device uses a 80 Angstroms thick SiGe layer with 30% Ge, and a 60 Angstroms thick Si cap layer, and shows a 2x gain in transconductance and in drain current over the baseline PMOSFET in simulation. The proposed integration uses only two extra masks and a few minor process changes. A suitable SiGe epitaxy process was developed to fabricate the proposed device. An extensive characterization of the available non-selective RPCVD epitaxy process was performed using various characterization techniques at 680°C and controllable growth rate was achieved. After a large surface roughness was observed because of the Stranski-Krastanov (SK) growth mode, a reduction in growth temperature to 630°C was found necessary, and a new set of process conditions was determined. A process flow was designed with the developed epitaxy as the central process and devices were fabricated. Some process integration changes had to be made to ensure the thermal stability of the SiGe layer. Fabricated SiGe devices did not perform better than the control Si device due to mainly a high surface roughness caused by the loading effect, and was confirmed using TEM cross-sections. However, a method to remove the surface roughness from the device was successfully tested by the deposition of a Si seed layer prior to SiGe epitaxy. Feasibility of an integrable, high performance, low-cost, strained-channel PMOS device has been successfully demonstrated.