At-speed diagnosis of delay defects and delay variations

With manufacturing technology moving into the nanometer regime, new device reliability problems arise. Meeting timing constraints is one of them. The semi-conductor industry requires automated tools to quickly analyze design timing failures in various phases, such as first silicon, volume production, and after customer returns.; Design failure analysis is a two-step process. First, diagnostic algorithms provide a list of suspect locations. Next, physical failure analysis techniques find the causes of defects using invasive, time consuming manual procedures. Engineers work with mechanical tools, ripping the chip apart to try to determine the physical defect using sophisticated microscopes. Thus, it is critical for a diagnostic algorithm to precisely and efficiently locate any timing failures. The quality of the diagnostic algorithm directly affects the product's time-to-market as well as the overall cost of producing functionally correct and reliable electronic devices.; In this dissertation we focus on analyzing those factors that determine the quality of diagnostic algorithms, and present methods for improvement. We utilize circuit timing information and very limited physical layout information to improve the quality of diagnostic algorithms, and to understand the effects of physical failures even before analysis.; We analyze the single- and multiple-delay fault diagnosis problem and propose a new algorithm based on our analysis. We enhance its quality using passing and failure information from the tester, processing the failure information at various slower-than-nominal clock periods, and applying n -detection and timing-aware automatic test pattern generated (ATPG) sets. We propose a methodology to diagnose delay defects in presence of crosstalk delays. We present a simulation-based methodology to relate the suspect location to the specific physical attributes responsible for the failures. We also propose a silicon debugging methodology using our diagnostic algorithms. We collect the data from both the failing and passing designs on a wafer, then estimate the delay defect and variation locations using statistical methods.