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High-efficiency gate drivers for low-voltage CMOS dc-dc converters

Posted on:2008-09-18Degree:Ph.DType:Dissertation
University:Stanford UniversityCandidate:Mulligan, Michael DavidFull Text:PDF
GTID:1448390005465277Subject:Engineering
Abstract/Summary:PDF Full Text Request
The growth of the portable electronics industry has demanded improvements in dc-dc converter technology in order to increase battery lifetime and enable smaller, less expensive systems. For example, brighter, full-color displays and a demand for increased talk-time in cellular phones has placed power consumption at a premium. Since many portable devices operate in low-power standby modes for a majority of the time they are on, increasing light-load converter efficiency can significantly increase battery lifetime. Additionally, better light-load efficiency also increases converter power density by enabling the use of smaller passive filter components.; In this work, we have developed two gate-drive techniques that can be used either alone or in tandem to improve the light-load efficiency of switchmode power converters. The first technique exploits the second-order overshoot of an underdamped RLC network to store and reuse a significant portion of the power MOSFET gate charge. Passive devices that are used in the charge recycling network can either be integrated or discrete components. A calibration step, which can be performed at system start-up, is implemented to maximize the amount of charge recycled.; In the second method we aim to optimize the trade-off between gate-drive loss and conduction loss in order to more efficiently actuate the power devices. We show that the optimal gate swing value scales with the load, and introduce straight-forward control methods for achieving autonomous operation with near-optimum performance. We also discuss the combined operation of these two gate drive methods, including key changes to the control and calibration subsystems.; To verify these concepts, a synchronous buck dc-dc converter was designed in a 0.5mum CMOS technology. The chip was tested over various conditions of switching frequency, input voltage, output voltage, and load. Converter power loss at light loads is shown to be significantly reduced, sometimes by as much as 30%, with efficiency improvements of nearly 8% for nominal conditions.
Keywords/Search Tags:Converter, Efficiency, Dc-dc, Gate
PDF Full Text Request
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