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Novel embedded testing methodology for mixed-mode integrated systems

Posted on:2008-09-25Degree:Ph.DType:Dissertation
University:University of RochesterCandidate:Liobe, JohnFull Text:PDF
GTID:1448390005974596Subject:Engineering
Abstract/Summary:PDF Full Text Request
The integration of RF subsystems with their baseband analog, mixed-signal, and digital counterparts has been fueled by the increased demand for high speed communications products. However, this union has exponentially amplified the testing and verification complexity for these mixed-mode ICs. These once separate domains are now being fabricated on the same piece of silicon, raising reliability concerns, especially as technologies continue to scale. To exacerbate matters, contact-based testing methods are not available due to the limited available area and the potential intrusive behavior of the test probes. External testers, although very accurate, are not economically viable because of the exorbitant amount of capital and testing time required by their implementation. Built-in testing (BIT) solutions have emerged as possible remedies to this conundrum, whereby the testing functionality has been pushed closer the device-under-test (DUT). However, due to all the associated challenges, an efficient and comprehensive testing methodology for these mixed systems has yet to be discovered.; A defect-oriented, analog-to-digital converter-based (ADC) testing methodology has been demonstrated that attacks this problem from two separate fronts. Extraction of both catastrophic and parametric fault information is attained from two DUT parameters: voltage gain and supply current. The crux of this solution is focused around a high-performance ADC and current sensor, both of which are resilient to a varying operating environment. In order to verify the accuracy of the test configuration, novel ADC and phase-locked loop (PLL) BIT solutions are also presented. By implementing this scheme as a "first pass" characterization early in a production line test flow, a high fault coverage has been demonstrated for the benchmark circuits included here, while reducing test times significantly and gaining internal device observabilty without sacrificing excessive overheads.
Keywords/Search Tags:Testing
PDF Full Text Request
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