A system-level platform-based multi-core system-on-chip simulation framework with retargetable processing element models

Today's semiconductor technology makes it reality to integrate up to billions of transistor to create the complete system on the single silicon die. The escalating design complexity makes the traditional register transfer level (RTL) design and modeling methodology inadequate facing the pressure of time to market and limited resource. Electronic system level (ESL) design methodology is needed to handle such a complex system-on-chip (SoC) design. System level modeling is core to this new methodology. This work explores system level modeling of function, performance and power and proposes a complete hierarchical SoC simulation framework supporting heterogeneous processing elements (PEs) integrated with a network-on-chip (NoC) communication infrastructure.; To efficiently map an application onto multiple heterogeneous PE architectures, an object-oriented application/task model is proposed. PEs are characterized by their macro-models for both execution time and energy consumption. Performing macromodel back-annotation to application tasks enables fast and cycle-approximate timing and energy simulation. Moreover, the resulting retargetable PE model methodology mitigates the effort of task remapping among different core architectures by using the uniform macro-operation set. Task scheduling engine (TSE) and Task execution engine (TEE) supports dynamic task scheduling. By this method, the task-level simulation can be taken without architecture-dependent cross-compilers/synthesizers.; The parameterizable NoC model features configurable routers and links. All the internal operations in each component are modeled as transaction-level function calls. Analytical transaction-level dynamic and leakage energy models are developed for each NoC component, and energy estimation is triggered whenever there is a transaction during the simulation. The NoC model also supports temporal and spatial power profiling that will help designers identify the potential hot-spots during application simulations. By configuring the four architectural parameters, NoC with different on-chip routers is evaluated. A complete SoC simulation framework is developed with the case study of M-JPEG application. The power/performance evaluations are performed to prove the effectiveness of the proposed modeling methodology.; Based on the proposed simulation model, a system-level SoC design space exploration framework is developed with the novel in-loop simulation feature. The principle it employs is to minimize the on-chip communication size while meeting the throughput constraints. And local architectural fine-tuning of PE/NoC is also applied to achieve the further power savings.; Overall, this methodology will bring significant changes in the way how future system-on-chips are designed. The inherent scalability enables the tradeoff of modeling time and accuracy. It has broad applications, from early design space exploration, through design refinements and iterations, to design characterization and reuse.