Power-aware design in modern computing systems

As the result of the increased device integration and IC design complexity, power consumption becomes an important design constraint and major barrier for technology scaling. Meanwhile with the advent of mobile computing devices, and with the new trends towards embedded and system-on-a-chip computing, power-awareness becomes one of the primary design goals for mobile computing systems. In data-driven computing system, storage device plays a more important role in determining their performance. High performance requirement leads to high power dissipation which again leads to high temperature. Since temperature has a significant impact on system reliability and cooling cost, power aware design for storage system is gaining more importance. I/Os and buses also consume a large amount of power because of large load capacitances. As technology scales to sub-micron dimensions, power dissipation due to coupling capacitances becomes the dominant factor, especially for long on-chip buses.; In this dissertation, I present several power-aware design techniques for three major components contributing to the total power consumption of modern computing systems: microprocessors, storage systems, I/Os and buses. First, a micro-architectural level leakage model is presented. It is based on transistor-level simulations and the effects of temperature, supply voltage, threshold voltage and parameter variations are included which allow designers to explore various leakage control techniques in caches. Second, to achieve energy optimization of microprocessors in real time systems, a procrastinating voltage scheduling algorithm is presented. It utilizes the statistic information of workloads and minimizes the energy for frame-based real time applications. Third, to achieve energy and performance optimization in storage systems, a comprehensive power and performance model based on physical nature of hard disk systems is developed. Based on this model, a sensitivity-based optimization method is presented for disk architectures. Fourth, to reduce power consumption on buses, a bus encoding technique is presented to reduce couple power consumption between adjacent wires. Finally, since circuits can experience a wide temperature range, an adaptive technique is to mitigate the impacts of temperature variations which can be applied in parallel with other power-aware techniques.