Design Considerations of Graphene FETs for RF Applications

This dissertation discusses various physical aspects of graphene electronic devices, particularly FETs, of importance for high frequency (RF, microwave and mm-wave) applications. Device physics of graphene junctions and contact junctions are considered. Inhomogeneity effects, heat dissipation and graphene FET compact modeling including unique nonlinearity mechanisms are discussed.;The first part of the dissertation discusses device physics of graphene. The importance of its unique band structure, high carrier mobilities, and maximum current handling are highlighted for RF applications. Graphene junctions are discussed in detail, including p-n junctions and graphene-to-metal junctions. It is shown that graphene p-n junctions provide additional resistance at the transition region within representative FETs due to depletion of carriers, which results in asymmetric ambipolar Id-Vg curves. It is also shown that a charge transfer region is formed at metal-graphene edges, which produces errors in the customary contact resistance measurement and analysis. Both junction effects are controlled by carrier density of the film, fringe electric field, and bias conditions.;Inhomogeneous graphene films are modeled in detail to describe the formation of electron-hole puddles, and their impact on Hall mobility measurements. Inhomogeneity is more significant with larger amplitude of random charge fluctuation and the size of puddles. It is shown that measured Hall mobility can be degraded by more than 8 % due to inhomogeneity, compared with ideally uniform films with the same average carrier density.;Thermal properties of graphene FETs must also be understood in relation to their performance and reliability. Heat dissipation of graphene devices has been analyzed with 3-D thermal simulations. The significance of interface thermal resistance, device design for quick heat release, and contact metal use for lateral heat spreading is described. Simulation and experimental results showed that pulses as short as 200 ns can still heat up graphene devices due to their small heat capacity.;Finally, graphene device models are developed in two forms: a SPICE-like compact model for straightforward usage in circuit simulators, and a more abstract analytic model for investigation of the impact of device parameters on circuit performance. Both device models are used to explore the performance of graphene-based FETs in zero bias r.f. power detector and resistive linear mixer applications. Parasitic elements such as parasitic capacitances, gate and series resistances are included for realistic circuit simulation, and the role of these components on the circuit performance is investigated. Graphene-based zero-biased power detectors showed sensitivity comparable to those using CMOS and InP HEMT-based technologies. Simulated noise equivalent power (NEP) was estimated to be as low as 10 pW/Hz0.5 for a passive r.f. power detector, thanks to the suppression of flicker noise. The mixer also exhibited linearity comparable to state-of-the-art, with input third-order intercept point (IIP3) estimated at about 22 dBm. Simulation results describe the experimental results well. The impact of different device design parameters are investigated by simulation in order to optimize performance.