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Hysteretic modulation for point of load application

Posted on:2007-11-16Degree:Ph.DType:Dissertation
University:University of FloridaCandidate:Mishra, Santanu KFull Text:PDF
GTID:1452390005986810Subject:Engineering
Abstract/Summary:PDF Full Text Request
Advancement in semiconductor technology has enabled the modern communication and data processing integrated circuits (ICs) to improve speed and integration density. The power supply to these ICs is continually required to deliver power at lower voltage and with stringent regulation requirements. Dynamic behavior of the power supply is normally improved by feeding the dynamic variables, such as the inductor current and the output voltage of the converter, into the pulse width modulator (PWM). Very fast dynamic response can be achieved by using both the peak and valley of the output voltage ripple to determine the switching instants, leading to the class of hysteretic modulators.; The requirement to have lower supply voltage for the ICs also tightens the output voltage ripple requirement. In order to meet these requirements, capacitors with small equivalent series resistance (ESR) are used. This makes the natural output voltage ripple of the supply very small and corrupted for proper hysteretic operation. This dissertation describes a modulation scheme for modulator carrier wave generation from converter voltages with added dynamic variables. The resulting hysteretic modulator, identified here as the synthetic ripple modulator (SRM), allows proper hysteretic operation even with very small and noisy output voltage ripple.; The steady-state operation of the SRM is derived and experimentally validated. Critical design parameters affecting the steady-state operation, such as the switching frequency, are quantified and validated. Small signal modeling technique is applied in order to characterize the dynamic behavior of the modulation scheme. Design equations are developed to device a comprehensive design technique for optimized transient response with minimum number of output capacitor. Average models are developed to help predict the steady-state and dynamic behavior of the modulator for faster simulation with minimal computational time.; A synchronous buck converter with a 10.5 V input and 1.8 V/15 A output rating is designed to verify the steady-state and dynamic equations. The response of the VRM to dynamic load transition is verified with a 15 A load current step at a slew rate of 15 A/mus. Transients results show a 65 mV step-down overshoot and a 37 mV step-up undershoot in output voltage, which matches very closely with the perdition. Results prove the superior response speed of the SRM without the inherent problems of the conventional hysteretic modulators.
Keywords/Search Tags:Hysteretic, Output voltage ripple, SRM, Modulator, Modulation, Load, Dynamic, Response
PDF Full Text Request
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