| To enhance the performance of ULSI chips, interconnection technology needs innovations such as copper/low-k dielectric (Cu/low-k) system and increasing layers of wirings. However, these innovations raise many challenging issues on reliability. This study is focused on the reliability of Cu interconnection structure including the grain structure of Cu and the early failure of Cu via. An earlier study on the Electro-Static-Discharge (ESD) robustness of aluminum (Al) based interconnection lines is also included.; Grain structure is a fundamental element determining the reliability of an interconnection. The evolution of Cu grain structure over processing steps, namely, the self-annealing of as-deposit state at room temperature and the texture evolution during subsequent thermal annealing are the initial subjects of this study. The difference of texture evolution between blanket Cu film and Cu line in a trench structure has been observed and explained based on the results of thermal stress simulation.; In order to investigate the cause of early electromigration failure in Cu vias, an infrared (IR) microscope technique has been developed to detect a weak via before catastrophic failure. Among various probable factors, a pre-existing defect is essential to the formation of an electromigration induced void. A crack in the barrier layer at the corner of a via induced by thermal stress plays the primary role in the formation of a “weak mode” void, leading to the early failure. After an electromigration failure, the failed via could be healed. Failure analysis suggests that the recovery is a result of local melting or copper back-diffusion due to compressive stress at the anode side.; In traditional Al/SiO2 system, a concern is the robustness of a line under ESD type stressing. A Transmission Line Pulse (TLP) method has been used for stressing, and numerical calculations support failure analysis. A line could sustain latent damages even when stressed below the critical level necessary for destructive structure failure. This latent damage is developed due to the extremely short duration time of stressing (∼100nsec), which does not provide enough time and energy for the line to be completely melted down. A line with latent damages becomes very vulnerable to subsequent electromigration failure. |
