Electronic System Optimization Design via GP-Based Surrogate Modeling

For an electronic system with a given circuit topology, the designer's goal is usually to automatically size the device and components to achieve globally optimal performance while at the same satisfying the predefined specifications. This goal is motivated by a human desire for optimality and perfection.;This research project improves upon current optimization strategies. Many types of convex programs and convex fitting techniques are introduced and compared, and the evolution of Geometric Program (GP)-based optimization approaches is investigated through a literature review. By these means, it is shown that a monomial-based GP can achieve optimal performance and accuracy only for long-channel devices, and that a piecewise linear (PWL)-based GP works well only for short-channel, narrow devices without many data fitted. Based on known GP optimizer and convex PWL fitting techniques, an innovative surrogate modeling and optimization algorithm is proposed to further improve performance accuracy iteratively for a wide transistor with a short channel. The new surrogate strategy, which comprises a fine model and a coarse model, can automatically size the device to create a reusable system model for designing electronic systems and noticeably improving prediction accuracy, particularly when compared to the pure, GP-based optimization method.;To verify the effectiveness and viability of the proposed surrogate strategy, a widely used two-stage optimization design is employed, entailing an operational amplifier (op-amp) and LC-tuned oscillator. In addition, an involved analysis and simulation demonstrate that the optimal results of both coarse and fine models in the proposed surrogate strategy may gradually converge to each other iteratively while achieving over 10% improvement in performance accuracy compared to the previous, PWL-based GP algorithm. As a result, the proposed surrogated modeling and optimization algorithm can serve as an efficient Computer Aided Design (CAD) tool, with the capability of dramatically improving performance for Integrated Circuit (IC) design.