ESD protection circuits for advanced CMOS technologies

Electrostatic Discharge (ESD) has become one of the most critical reliability issues in integrated circuits (ICs). In this dissertation, a variety of ESD issues in advanced complementary metal-oxide-semiconductor (CMOS) technology are discussed, covering topics that range from fundamental device physics to analog circuit design.; The impact of ESD parasitic elements on the performance of radio frequency (RF) ICs is analyzed. Based on 2-GHz narrowband and 5-GHz broadband low noise amplifiers, the concept of RF ESD co-design is used to study the limitations of conventional low-capacitance ESD protection. Results show that at relatively low frequencies (below 5 GHz) low-capacitance design methods can be effectively adopted. However, for extremely high frequency applications, only co-design methodologies can provide the needed ESD protection capabilities without substantial degradation of RF performance.; Nonlinearity of the capacitance associated with ESD protection devices can introduce signal distortion in high performance mixed signal ICs, such as analog-to-digital converters. This dissertation provides a theoretical analysis and experimental results that quantify the resulting distortion levels. It is shown that with spurious free dynamic range (SFDR) targets approaching 100 dB at frequencies near 100 MHz, the ESD protection device can become a performance-limiting factor.; A new ESD failure phenomenon of PMOS devices is analyzed. Localized turn-on of the parasitic PNP transistor can be caused by localized charge injection from adjacent diodes, thereby degrading ESD robustness. The critical layout parameters affecting this problem are identified and design guidelines for avoiding this issue are proposed.; To extend the use of commercial technology CAD (TCAD) tools into the sub-100 nm regime, ESD protection capabilities of strained-Si/SiGe devices are investigated to account for electrothermal effects. Despite the low thermal conductivity of the SiGe layers, strained-Si devices are found to have superior ESD protection capabilities when compared to unstrained-Si devices.; A new electrothermal model for the simulation of nano-scale devices is developed. This model is validated based on simulations of a thin-body silicon-on-insulator (SOI) transistor. The developed system of model equations captures most of the physical phenomena of the heat generation and conduction inside nano-scale devices with only moderate numerical complexity.