Memory design for robust and energy-efficient computing systems

On-chip random access memory (RAM) area/capacity increases every technology generation in order to reduce accesses to external memories that require long latency and high energy consumption. However, large on-chip read only memories (ROMs) have not been traditionally used, perhaps because of its limited usage and space availability. This research proposes a ROM-embedded cache memory at no extra area cost for the ROM. We consider two different technologies: CMOS and spin-transfer-torque based magnetic RAMs. We show that conventional standard 6T and 8T SRAM bit-cells can embed ROM data without area increase or performance degradation on the bit-cells. Just by adding an extra word-line (WL) and connecting the WL to selected access transistor of the bit-cell, the bit-cell can work both in the SRAM mode and in the ROM mode. We also show that STT MRAM can store additional ROM data without area increase in a bit-cell using selective bit-line connectivity. We present architectural supports to implement ROM-embedded cache using SRAM and STT MRAM. As example applications of ROM-embedded cache, we explore fast evaluation of mathematical functions and low-cost logic test along with a new logic test data compression architecture based on Viterbi algorithm. We also propose circuit/architecture techniques to enable STT MRAM to be a promising on-chip memory. Due to inherently high write current and significant asymmetry of switching times, STT MRAM suffers from high write time/energy. Our proposed biasing schemes and two-step write operation can reduce write energy wastage and improve write performance without increasing bit-cell size.