Characterization of nanoscale local lattice strains in silicon CMOS devices by TEM/CBED

Strained-Si technology has become one of the leading approaches to further improve the performance of the metal-oxide-semiconductor field effect transistors (MOSFETs) as traditional device scaling faces its physical limitation. In particular, mechanical strain induced in the Si channel region is used to increase the carrier mobility and the transistor drive current. To be able to understand and engineer the local lattice strain incorporated in the nanoscale device region, a strain measurement technique with high spatial resolution and high sensitivity is essential. Currently, transmission electron microscope (TEM)/convergent beam electron diffraction (CBED) is the only method to measure local changes in lattice parameters due to strain in advanced CMOS devices, because this technique provides nanometer spatial resolution and strain sensitivity on the order of 10-4.; In this study, a novel experimental methodology is developed to measure the strain effectively and efficiently. Site-specific TEM samples are prepared by focused ion beam (FIB) with controlled thickness. Zone axes such as <230>, <340>, <560> and <910> are evaluated for obtaining CBED patterns. The specimen-tilt projection and dynamical effects related to the zone axis are discussed. CBED pattern simulation and matching procedures are explained to extract the strain tensors. The accuracy of the strain measurement depends on the clarity of the CBED pattern, which can be improved by using an energy-filter or sample cooling stage.; The direct strain measurements are performed in sub-100 nm CMOS devices with either structure-induced or process-induced strains. It is found that the compressive strains are induced when the shallow trench structure (STI) is filled with isolation films. The compressive strains on the order of 10 -3 are observed under the gate region in a Si <110> PMOS transistor with a 37 nm gate length. One-dimensional quantitative strain-mapping is demonstrated using the nanometer probe. The tensile strains under the gate in a Si <100> channel NMOS transistor are determined using the <910> zone axis for the first time. It is found that the tensile strain increases with the thickness of the silicon nitride capping layer, which is consistent with the device's electrical behavior. The carrier mobility enhancement caused by the uniaxial tensile strain results in a drive current improvement up to 27%. The process-induced strain relaxation is observed in the device during the subsequent implant and anneal steps, as compared to the unprocessed device. In the Si1-x Gex/Si heterostructure wafer, the HOLZ line splitting and blurring are suggested to be attributed to the strain relaxation from the thin TEM sample and high strain gradient.