Automation of Simulation-Based Verification at the Register Transfer and Behavioral Levels

Even with the end of Moore's Law in sight, designs are not only becoming larger with higher complexity but more ubiquitous and numerous. Applications in the medical, environmental, consumer products, space exploration, defense, and governmental industries have seen a rise in the number of large systems for "big data" processing and small embedded systems with application-specific uses. In order to meet this growing demand for technology, the models must meet this level of complexity with higher levels of abstraction. Moving beyond register transfer and cycle accurate levels, a new paradigm of behavioral and specification level models and methodologies are being researched in hardware engineering in order to satisfy these ever-shifting needs of high functionality.;The complexity of algorithms and methods to verify these systems pose an even greater challenge as design implementations grow and change. Two prominent methods of verifying a system is by using formal methods of verification and simulation-based validation.;In this dissertation, I present two techniques, one that minimizes the impact of the human factor in comparing verification techniques in model checking and simulation and another that automates the creation of a testbench framework. In the first technique, I present a verification evaluation strategy for comparing model checking/equivalence checking with simulation-based verification in order to find the area of highest impact in the field. Discovering that simulation-based verification provided comparable results to that of model checking, I elected to focus my research in this area. I develop automation techniques in the verification of hardware designs written at the register transfer level [RTL] with techniques in testbench generation and response checking at the specification level. The evaluation framework utilizes standard benchmark designs with a proven method for accuracy with the use of automation in the comparison of equivalence checking and simulation-based techniques. I argue that our automated behavioral level functional verification techniques in testbench generation and response checking target specification-level errors not found within other approaches. I define and model the testbench and response checking designs automatically with the use of higher level models that preserve and utilize specification level constructs.