Design techniques for 40Gb/s broadband CMOS communication circuits

To satisfy the bandwidth demands of global digital communications traffic, speed requirements for telecommunication systems are continually increasing. Current state-of-art systems are running at about 10Gb/s. The next generation system will operate at 40Gb/s and above. Such high bit rates pose particularly challenging technology and design issues. Recent implementations of a 40Gb/s MUX/CMU have been realized mainly in high speed InP and SiGe technologies.; With aggressive scaling, modern CMOS technologies have the potential for use in serial communication systems operating at data rates well above 10Gb/s. As compared to other processes, CMOS has the advantage of lower power dissipation and higher integration capability. In this dissertation some innovative circuit techniques are discussed that make it possible to implement these high speed circuits in readily available and less expensive 0.18mum CMOS process.; It has been shown that the high-frequency performance of conventional CML circuits can be improved by using on-chip inductors. For circuits processing broadband data signals a circuit technique called inductive peaking can be used to improve the bandwidth by about 60%. For single-frequency clock signals resonant peaking technique is used to provide amplification and carry high-speed clock signals to the load. To improve the speed of CML circuits even further, a different approach based on distributed amplification has been introduced. This technique is shown to give a notable improvement in the gain-bandwidth characteristics of the individual devices.; To demonstrate the practical usability of the above techniques a serializer (including clock multiplier unit) operating at 34Gb/s was designed using 0.18mum CMOS technology. The crucial and challenging circuit to design in a high-speed serializer is the final 2:1 select circuit which operates at full-rate. A distributed amplifier topology was used to achieve the speed of 34Gb/s, which is the highest reported to date in a similar technology. Inductive peaking and resonant peaking techniques were used to realize the rest of the circuit. The ISI of the serial output was measured to be less than 5ps p-p and random jitter was about 940fs rms. The phase noise of the 17GHz clock at 1MHz offset was -100dBc/Hz and the jitter generation was measured to be 240fs over a 50kHz to 80MHz bandwidth. The total power dissipation of the serializer is 450mW with a 2.0V supply voltage. The total chip area is 3000mum by 2000mum.