Hardware-accelerated signaling: Design, implementation and implications

Despite the dominance of connectionless IP networks, i.e., the Internet, connection-oriented networks are gaining attention because of their inherent support for Quality of Service (QoS). Even IP routers are being enhanced with connection-oriented features. Signaling protocols are used in connection-oriented networks to set up and tear down connections.; Signaling protocols are primarily implemented in software for two reasons, complexity and the requirement for flexibility. Although these are two good reasons for software implementations, the price paid is in performance. Software implementations of signaling protocols are rarely capable of handling over 1000 calls/sec. Correspondingly, per-switch call processing delays are in the order of milliseconds.; We propose to implement signaling protocols in hardware, expecting a 2--3 orders of magnitude improvement in the call handling capacities of switches. As a first step, we define Optical Circuit-switched Signaling Protocol (OCSP), a performance-oriented signaling protocol designed for SONET switches. We implement OCSP on WILDFORCE FPGA evaluation board. The simulation results show a call handling rate of 150, 000 calls/sec and a per-switch call processing delay of 6.6mus.; We then choose RSVP-TE for hardware acceleration. As a signaling protocol targeting almost all connection-oriented networks, RSVP-TE for GMPLS is complex and flexible, and not intended for hardware implementation. However, it is not only impractical but unnecessary to implement the complete signaling protocol in hardware. Instead, we extract a subset of RSVP-TE for hardware-acceleration and relegate the functionality beyond this subset to software. The subset is large enough to cover time-critical operations while small enough to make hardware implementation feasible. We implement the subset on a Xilinx Virtex-II FPGA device, which we call hardware signaling accelerator. With a fully pipelined architecture and innovative design techniques, a call handling rate of 250, 000 calls/sec is achieved, and per-switch call processing delay is 7.2mus.; In order to demonstrate a complete switching system equipped with the hardware signaling accelerator, we design a PCI-based prototype board including both user-plane and control-plane devices. The user-plane carries the user traffic while the control-plane controls the operation of the user-plane. The hardware signaling accelerator is the core component on the control-plane.; The total call setup delay consists of three components: round-trip propagation delay, call processing delays, and signaling message emission delays. (Abstract shortened by UMI.)...