A systems approach to ultra-fine pitch flip chip interconnect packaging

Flip Chip (FC) technology is a key enabler for high-density, high input-output (or I/0) applications and is one of the fastest growing segments in the semiconductor packaging industry.; The objective of this research was to explore the feasibility of packaging high-I/O, ultra-fine pitch reflow soldered flip chip devices of the future with a pitch of less than 150 mum. The applications addressed in this research include devices that typically utilize flip chip ball grid array (or FCBGA) packaging technology. The limits of the flip chip reflow solder technology have been explored in terms of interconnect feature sizes and the related assembly, functional, and electrical implications. The entirety of this research has been based upon a combination of experiments and the use of theoretical approaches. The impact of reducing the interconnect size on factors that affect the assembly yield was studied. The solder joint formation process was modeled and validated using an interactive program called 'Surface Evolver'. This program can be used to predict the shape of a liquid surface by evolving it toward the minimal energy using a 'gradient descent' method. The effects of reducing interconnect size on placement accuracy, solder bridging, and self-alignment were analyzed. The impact of using lead free solder was evaluated. A detailed analysis of parameters that control the assembly yield in the no-flow underfill process was also carried out.; The results indicate that solder bump geometry and package I/O count can have an impact on solder joint collapse. Solder bump volume does not strongly affect the extent of collapse and the self-alignment capability. On the other hand, in presence of a no-flow underfill, the self-alignment capability is expected to reduce with the solder bump volume. The self-alignment capability also strongly depends on the viscosity of the underfill.; Theoretically, the impact on the solder joint collapse due to the use of lead free solder was observed to diminish with reducing solder bump volume. The analysis of placement and fabrication tolerances revealed relatively strong reduction in the placement tolerance due to a small reduction in the solder bump size. The placement tolerance can be relieved by modifying the geometry of the coverlay opening.; A case of packaging a high I/O flip chip with minimum number of layers of circuitry has also been evaluated in this research. The electrical implications have been addressed, which include impedance, crosstalk, and transmission line analysis. In addition, the effect of reducing solder bump volume on the phenomenon of electromigration has been briefly studied.; In conclusion, this research highlights the system level design and assembly issues in ultra fine pitch reflow soldered flip chip packaging. The significance of this research is that the problem is addressed through multiple perspectives, which includes evaluation of the solder joint formation process, issues pertaining to the fabrication and assembly of the package, and impact on the electrical performance. (Abstract shortened by UMI.)...