Security and testing

This dissertation presents research on improving the security of computing platforms at a physical and logical level. The main contributions are to improve the security of: (1) test data communication between chips; (2) test data communication within chips; (3) communication between sensors and chips; (4) verification of chip authenticity.;We investigated the security of IEEE 1149.1 JTAG and studied existing attacks. We invented two new attacks and experimentally verified them. After generalizing the threats, we designed and implemented a security-enhanced backwards compatible version of JTAG.;We identified security vulnerabilities that stem from the use of shared test on-chip test data wiring in system-on-chip (SoC) designs, particularly where trusted and untrusted cores coexist. We developed an efficient architecture and protocol that mitigates test-related risks.;We extended the concept of the physical unclonable functions to encompass sensors. The result is a sensor whose measurement can be verified by the logic inside the trust perimeter.;We propose countermeasures to the growing problem of counterfeit components. We developed an inexpensive end-to-end scheme for ensuring the authenticity of parts received by a system integrator.;The four platform security enhancements we developed complement each other. They solve non-overlapping problems that exist today and they can be applied individually or together. Applied together, they significantly raise the bar for platform security.