Virtual-ground sensing techniques for fast, low-power, 1.8V two-bit-per-cell flash memories

Fast and accurate read operation in 1.8V, two-bit-per-cell virtual ground flash memories requires techniques to substantially reduce the read margin loss due to the adjacent cell leakage current, the complementary-bit disturbance and also due to the cycle-induced mobility degradation. The read margin loss caused by the combined effect of these three disturbance factors is serious enough to eliminate the read margin window, which is already small when the power supply voltage is about 1.8V and when each memory cell stores 2 bits. This work introduces for the first time the sense current recovery technique to counteract the adjacent cell leakage current effect, the differential feedback cascoded control of bitline voltage to minimize the complementary-bit disturbance, and the auto-calibrated control of the wordline voltage in the read mode to reduce the mobility degradation effect as well as to ease the design of the sensing circuitry. A 1.8V, 256Mb, two-bit-per-cell virtual-ground flash memory employing all three techniques has been integrated using 0.13μm nitride-storage technology. These three sensing techniques are essential for the memory in order to achieve 30.4ns initial read access and 200MHz internal burst sensing speed. The die size for the prototype test chip is 52mm2 and the cell size is 0.121μm2.