Design and analysis of on-chip high performance power distribution networks

Distributing power in modern high speed, high complexity integrated circuits has become a challenging task. State-of-the-art circuits draw tens of amperes of current from a low voltage power supply, while switching on-chip loads within tens of picoseconds. These conditions place strict requirements on the impedance characteristics of the on-chip power distribution networks to ensure the integrity of the on-chip power supply levels.; The impedance characteristics of on-chip power distribution grids are analyzed in this dissertation with the emphasis on the inductive properties crucial for high speed operation. The impedance characteristics of single-layer grids are analyzed first. In the grids with alternating power and ground lines, the long-range magnetic coupling cancels out, rendering the inductive coupling an effectively short-range phenomenon. Consequently, the inductance of the grids, similar to the grid resistance, varies linearly with grid dimensions. Variation of the grid inductance with frequency is also analyzed. Inductance of single-layer grids varies slowly with frequency due to a regular structure of the grids. The tradeoffs among the resistance, inductance, and area of the grids are explored. Analytic expressions are developed to evaluate the grid inductance in an efficient manner based on the pitch and cross-sectional dimensions of the grid lines. Finally, the impedance characteristics of multi-layer power distribution grids are analyzed. Unlike single-layer grids, the inductance and resistance of multi-layer grids vary significantly with frequency due to disparate impedance characteristics of the comprising grid layers. The inductance of a typical multi-layer grid decreases with frequency while the resistance increases with frequency, thereby maintaining a relatively low impedance over a wide range of frequencies. Multi-layer grids are therefore well suited for high speed, low impedance power distribution systems. A simple model for estimating the impedance characteristics of multi-layer power distribution grids is developed. The techniques and methods of analysis developed in this dissertation support the effective design of robust power distribution networks for application in high speed, high complexity integrated circuits.