Architectural Applications of Radio Frequency Interconnect for Chip-to-DRAM Communication

The demand for off-chip bandwidth to DRAM will continue to grow as we integrate more cores onto a die. Traditional interconnects are not sufficient to meet these demands. Emerging alternative interconnects, like Multiband Radio Frequency Interconnect (MRF-I), have the potential to provide the bandwidth and low power to meet the demands of future many-core processors. In this work we demonstrate the benefits of using MRF-I for chip-to-DRAM communication in terms of higher throughput, low power, and better scalability to a many-DIMM DRAM system. We modify existing DIMM architectures to use MRF-I with our MRF-DIMM. With MRF-DIMM, we are able to increase throughput by 107% on average (up to 126%) in a 4-DIMM system with better throughput/watt (by an average of 10%). In order to improve the bandwidth utilization of MRF-DIMM, we propose adaptive channels. Adaptive channels reconfigures the RF channels based on the application demand, increasing bandwidth utilization. We also propose the DIMM tree architecture for better scalability, and utilize MRF-I to increase throughput at low power, and scale to an even larger number of DIMMs. The DIMM tree architecture was able to increase throughput by an average of 68% (up to 200%) with 64 DIMMs and MRF-I using 4 RF bands per pin over a conventional DRAM system with 4 DIMMs. The DIMM tree architecture also only consumes 5% more power compared with a conventional DRAM system. Without MRFI, we were still able to scale to 64 DIMMs on a single channel with little degradation in throughput. We also propose the partitioned DIMM tree to allow scaling of the DIMM tree architecture to even more DIMMs by using the faster levels of the DIMM tree as a cache for the slower levels. With the partitioned DIMM tree, we are able to improve the throughput of a 256 DIMM system by an average of 19% up to 35%. Finally, we propose using MRF-I with intelligent scheduling to improve the throughput per watt of mobile GPU memory systems. With our intelligent scheduler and MRF-I, we are able to improve throughput per watt by an average of 18% up to 26%. Our combined contributions in this work create a complete demonstration of applying MRF-I for chip-to-DRAM communication to the desktop, notebook, server, and mobile markets for high throughput, low power, and scalability.