High frequency voltage controlled ring oscillators in standard CMOS

This dissertation presents a study of high-frequency low-noise CMOS voltage-controlled ring oscillators. The objective is to understand the limitations of voltage-controlled ring oscillators that are implemented in standard CMOS technologies when they are extended to multiple gigahertz applications. This study explores the maximum frequency limitations and the associated noise performance levels of ring oscillators that can be constructed using different design styles. Important metrics also include the tuning range, linearity of frequency-control characteristics, stability across temperature and process corner variations, and power consumption of the circuits. Simplicity and the low cost provide the main motivation for selecting a ring structure over competing LC-based architectures.;To fulfill the requirements of this study, various ring and LC oscillators were designed in several state-of-the-art CMOS processes. A multiple-pass differential architecture along with a saturated-type delay-stage utilizing cross-coupled transistors has been found to have promising characteristics. A new ring oscillator design, which mixes the analog and digital elements, is proposed to solve the problems related with the single-ended control and the high gain of conventional ring oscillator designs. By using these techniques, it may become possible to extend the applications of ring VCOs into some areas that previously required the performance of LC oscillators.