Low power SRAM cells and architectures for cache design

Low-power SRAM memory design is a crucial part of many applications. On-chip cache represents a large portion of the chip and it is expected to increase in the future in both portable devices and high-performance processors. To achieve higher reliability and longer battery life for portable application, low-power SRAM array is a necessity. There are different sources of active and stand-by power consumption in SRAM. The sum of the power consumption in decoders, bit lines, data lines, sense amplifier and periphery circuits represents the active power consumption. The power dissipated in bit lines represents 70% of the total dynamic SRAM power consumption during a write operation. In SRAM, the write methodology depends on discharging/charging large bit lines capacitance, which causes high power consumption. In this work, we develop four techniques to achieve a low power SRAM. Two of the four techniques depend on reducing the accessed bit line capacitance during a write operation, and therefore they reduce the write power consumption. The other two techniques target low power SRAM cell design which either reduces the activity factor of discharging the bit line or reduces the voltage swing on the bit line during a write operation. In all proposed architectures and cells, the cell properties, i.e. read delay and static noise margin SNM, are maintained.