Statistical models, methods, and algorithms for computer-aided design for manufacturing

Among the most challenging problems facing semiconductor industry is making the future electronic systems manufacturable. Advances in technology increase the magnitude and complexity of manufacturing variability. At the same time, circuits require less sensitivity to any deviation from the assumed process conditions. Design and manufacturing become inter-linked as never before, and failure to address the problem leads to malfunctioning and under-performing circuits. Statistical design and design-for-manufacturing are concerned with finding ways to perform robust circuit design in the face of manufacturing uncertainty. In this dissertation, novel statistical approaches to design-for-manufacturing are investigated.; As a first step, we need to identify the key, most sensitive, aspects of the design-technology interface. A model engine for decomposition of circuit performance variability to its causal contributors is developed. The results show that the device variability will continue to be the dominant source of the overall circuit variability.; An important component of the statistical design methodology is establishing the robust modeling link between the variations of the lower-level process and device parameters and the circuit and system-level properties, such as timing, power dissipation, and noise margins. Experimental characterization shows that state-of-the-art deep sub-micron CMOS technologies invalidate many previously used methods, requiring development of novel approaches to statistical modeling. A nonparametric direct sampling method for accurate statistical inter-chip circuit analysis is developed. In order to enable efficient statistical analysis of large circuits, a fast and accurate statistical algorithm is proposed. It extends the concept of directly sampled device models to the analysis of large circuits by introducing a hierarchical statistical modeling methodology.; In the early days of integrated circuits, the intra-chip parameter variability was not an important source of concern for design of digital circuits. Experimental analysis of a production 0.18μm CMOS process is presented. It shows the existence of a strong spatial variability of the CMOS gate length within the chip. A set of theoretical models is derived to analyse the impact of intra-chip variability on circuit performance and yield. It is found that in contrast to the effect of inter-chip variability, intra-chip parameter variation degrades the average circuit speed, shifting the entire chip speed distribution. Two algorithmic ways of dealing with intra-chip variability are proposed: mask-level compensation and location-dependent timing analysis. It is shown that spatial mask-level correction is an effective mechanism of reducing systematic variability and improving circuit speed.