Plasma-enhanced atomic layer deposition zinc oxide for multifunctional thin film electronics

A novel, weak oxidant, plasma-enhanced atomic layer deposition (PEALD) process has been used to fabricate stable, high mobility ZnO thin film transistors (TFTs) and fast circuits on glass and polyimide substrates at 200°C. Weak oxidant PEALD provides a simple, fast deposition process which results in uniform, conformal coatings and highly crystalline, dense ZnO thin films. These films and resulting devices have been compared with those prepared by spatial atomic layer deposition (SALD) throughout the work.;Both PEALD and SALD ZnO TFTs have high field-effect mobility (>20 cm 2/V·s) and devices with ALD Al2O3 passivation can have excellent bias stress stability. Temperature dependent measurements of PEALD ZnO TFTs revealed a mobility activation energy < 5 meV and can be described using a simple percolation model with a Gaussian distribution of near-conduction band barriers. Interestingly, both PEALD and SALD devices operate with mobility > 1 cm2/V·s even at temperatures < 10 K. The effects of high energy irradiation have also been investigated. Devices exposed to 1 MGy of gamma irradiation showed small threshold voltage shifts (<2 V) which were fully recoverable with short (1 min) low-temperature (200°C) anneals.;ZnO TFTs exhibit a range of non-ideal behavior which has direct implications on how important parameters such as mobility and threshold voltage are quantified. For example, the accumulation-dependent mobility and contact effects can lead to significant overestimations in mobility. It is also found that self-heating plays and important role in the non-ideal behavior of oxide TFTs on low thermal conductivity substrates. In particular, the output conductance and a high current device runaway breakdown effect can be directly ascribed to self-heating.;Additionally, a variety of simple ZnO circuits on glass and flexible substrates were demonstrated. A backside exposure process was used to form gate-self-aligned structures with reduced parasitic capacitance and circuits with propagation delay < 10 ns/stage. Finally, to combat some of the self-heating and design challenges associated with unipolar circuits, a simple 4-mask organic-inorganic hybrid CMOS process was demonstrated.