Selective chemical vapor deposition of heavily boron doped silicon-germanium films from disilane, germane and chlorine for source/drain junctions of nanoscale CMOS

As metal-oxide semiconductor field effect transistors (MOSFETs) are scaled for higher speed and reduced power, new challenges are imposed on the source/drain junctions and their contacts. Future junction technologies are required to produce ultra-shallow junctions with junction depths as low as 4 nm, above-equilibrium dopant activation, super-abrupt doping profiles and specific contact resistivity values below 1 × 10−8 Ω-cm2. Recently, selectively deposited, boron doped Si_1−xGe_x junctions have been proposed to overcome these challenges. Success of technology relies on selective chemical vapor deposition of the process and satisfying stringent requirements for process integration. In the present work, the effects of process conditions on selective deposition of heavily boron doped Si_1−xGe _x is investigated using Si₂H₆ and GeH₄ as the precursors.; It was found that addition of large amounts of diborane resulted in selectivity degradation. Addition of chlorine improved selectivity for both doped and undoped Si_1−xGe_x depositions. It was shown that addition of chlorine to the undoped Si_1−xGe_x deposition chemistry resulted in reduced surface roughness. It is proposed that chlorine preferentially segregates to the surface of the deposited films, and act as the surfactant. However, it was also found that addition of chlorine did not significantly impact the surface morphology of heavily boron doped Si _1−xGe_x.; It was shown that addition of chlorine strongly interfered with Ge and B incorporation. Furthermore, it was found that chlorine resulted in enhanced Ge but reduced B incorporation. It is proposed that chlorine adsorption on the growing surfaces reduced the available sites for boron while promoting SiCl₂ desorption at lower temperatures. Increase in deposition temperature for a given chlorine flow resulted in increased boron incorporation.; Planar MOSFETs with recessed junctions were fabricated using proposed technology. An isotropic plasma etch based on pure SF₆ was developed. The developed etch had lateral etch rate equal to ∼40% of the vertical etch rate. It was found that MOSFETs with low S/D junction off-state current and excellent subthreshold slope could be fabricated.