Fabrication of anodized tantalum oxide integrated capacitors on singulated chips with active devices

The purpose of this project was to determine the feasibility and processability of fabricating anodized tantalum oxide integrated capacitors on singulated chips. Using high-resolution transparencies to pattern the metals during the photolithographic process, capacitors as large as 0.25 cm2 were fabricated successfully with the yield being higher for capacitors smaller than 0.1 cm2. Several capacitor designed were attempted and final designed was selected on the basis of ease of alignment and prevention of shorts.; The next step in the project involved utilizing this design to fabricate capacitors on 2.2 mm by 2.2 mm silicon dummy chips. In order to accomplish this task, a support wafer technique was used. A silicon wafer with holes etched all the way through was attached to a non-etched silicon wafer to provide a base for the dummy chips that were placed in the holes of the support wafer, thus making the top of the chips co-planar with a wafer that could be put through standard wafer processing equipment. The chips were glued to the wafer using a thermoplastic as an adhesive.; The design specified for this project called for five 100 pF capacitors and a single 50 pF capacitor. Since the chips had to be individually placed in the holes, all the masks used in the project had to be individually designed for reach run. The capacitors had a bottom plate thickness of 2500 Å of tantalum which was anodized at 120 V and 0.5 mA/cm2 to an oxide thickness of 1920 Å. The top plate was 2 μm of aluminum and the insulating ring around the bottom plate was made of 5 μm of benzocyclobutene.; After fabrication, testing of the capacitors provided a yield of 97% for the 100 pF capacitors with average capacitance of 98.3 pF ± 3.6 pF and 75% for the 50 pF capacitors with an average capacitance of 50 pF ± 1.65 pF. The inductance of the capacitors was less than 20 pH and resistance was about 110 Ω. The resistance was brought down to 1 Ω when a 2 μm sublayer of aluminum was deposited under the tantalum bottom plate.; The final phase of the project dealt with the fabrication of the capacitors on individual working chips fabricated by MOSIS. The capacitors were part of the DC/DC converter designed to have an input voltage of 5 volts and an output of 15 volts. The chip also had MOSFET transistors that were tested before and after processing the MOSIS chips. Post-process test showed that the transistors survived the rigors of individual chip processing, but the DC/DC converter only provided an output voltage of 4.3 volts. The reason for this low voltage is not yet know but could be attributed to improper layout, incorrect chip fabrication, or capacitor processing issues.