Scaling CMOS memories

As CMOS approaches the 100nm node, logic remains a leading technology driver. But features in multi-gigabit memory technologies do not scale as easily. In DRAM, for example, the storage capacitance must be kept constant for soft error reliability, sensing signal margin, and data retention considerations while the transistor's threshold voltage is kept nearly the same to minimize charge leakage from the storage capacitor. Likewise, FLASH memories have a fixed tunnel oxide thickness for achieving ten year retention times.; To address these scaling challenges, the memory industry needs new ideas. Many novel ideas, such as ferroelectric memory, require new materials which have proven to be difficult to manufacture. This work focuses on new approaches to memory scaling with devices which use conventional CMOS materials. Chapter 1 discusses the key challenges in scaling conventional DRAM and FLASH memories. Chapters 2 and 3 present experimental results from two new capacitorless DRAM technologies: double gate DRAM (DG-DRAM) and direct tunneling RAM (DT-RAM). Scaling the tunnel oxide thickness in nonvolatile memories is examined using P+ floating gates, nanocrystals, and traps in chapters 4 and 5. Finally, new evidence is presented in chapter 6 to support a trap-assisted tunneling model which describes how drain voltage scaling affects channel hot electron programming in the presence of oxide traps.