Design and simulation of cellular nonlinear networks using single-electron tunneling transistor technology

It is currently predicted that semiconductor device scaling will end at the 22-nm device feature size (7 nm physical channel length) according to the International Technology Roadmap for Semiconductors. The main challenge is then to develop innovative technologies that will extend the scaling beyond roadmap projection. Any new technology must be well matched with complementary metal oxide semiconductor (CMOS) technology and scaleable beyond CMOS scaling projections and must provide low-power high-speed signal processing. Nanotechnology will become an appealing option for developing devices for integrated circuits with dimensions and performances well beyond roadmap predictions. Such devices, based on the controllable transfer of charge between dots or ‘islands’, can take advantage of the quantum mechanical effects, such as tunneling and energy quantization, which would normally occur at the nanometer scale. An outstanding challenge is in arranging such nanodevices in new architectures that can be integrated on a single chip. In particular, locally interconnected architectures are believed to be necessary to alleviate the problems associated with increasing interconnect length and complexity in ultra-dense circuits.; The goal of this work is to investigate the use of nanoelectronic structures in cellular non-linear network (CNN) architectures for potential application in future high-density and low-power CMOS-nanodevice hybrid circuits. The operation of the single-electron tunneling (SET) transistor is first reviewed, followed by a discussion of simple CNN linear architectures using a SET inverter topology as the basis for the non-linear transfer characteristics for individual cells to be used in analog processing arrays for image-processing applications. The basic SET CNN cell acts as a summing node that is capacitively coupled to the inputs and outputs of nearest neighbor cells. Monte Carlo simulation results are used to show CNN-like behavior in attempting to realize different functionality, such as connected component detector, shadowing, and NOT function. The speed and signal delay in SET networks are also discussed, and the power consumption of the SET-CNN is estimated and compared to a state-of-the-art CMOS processor.