Test selection and fault simulation for analog integrated circuits

The integration of analog circuits with digital components on the same die has brought the testing of such systems to the forefront. The lack of CAD techniques in this area has forced test engineers to design test programs manually, adding significantly to the manufacturing cost. This dissertation explores automation aspects related to the optimal selection of analog tests.; The optimal test selection is posed as an optimization problem and special techniques to solve this problem are presented. To evaluate the objective functions during optimization, computationally intensive circuit simulation is required, limiting its applicability to small analog circuits. To mitigate this problem we next investigate simplified fault macromodeling to improve simulation performance. We demonstrate the application of this technique on a sigma-delta A/D converter. However, the generality requirement imposed on circuit simulators is the limiting factor in improving simulation performance further. In the final part of the dissertation we present a specialized fault simulation technique for switched-capacitor systems producing up to two orders of magnitude improvements in the simulation time over traditional circuit simulation.