Testing signal integrity in high speed VLSI chips

Relentless demand of faster and more sophisticated systems incited the technology evolution which led to multi-billion transistors on a chip. The notion of a multi-billion-transistor system on a chip, though attractive and powerful, has its negative byproducts: it triggers the IC design productivity crisis and signal integrity perplexity. Of course, design and test complexities must grow together as technology progresses.; Long interconnects connecting functional blocks together give rise to signal integrity problems. In high frequency, a long wire behaves as a transmission line where electric and magnetic fields and waves equations are needed for accurate simulations. Various forms of capacitive and inductive coupling aggravate the complexity of signal integrity analysis.; Signal integrity distortions can harm a system in various forms. Functional behavior of a logic can be threatened by signal integrity violations. Performance degradation is another repercussion which can be sternly influenced by signal integrity noise. In addition to these direct adverse effects, signal integrity noise jeopardizes the reliability of chips. Frequent signal integrity violations can significantly reduce the life time of a chip. In this work, signal integrity and its adverse effects were extensively elaborated.; The complexity of signal integrity requires new design and test methodologies. It is no longer feasible to end design for test (DFT) efforts at the RT-level. This requires developing methodologies to recognize integrity-sensitive nets. These nets are to be equipped with test circuitry which carefully monitor the behavior of interconnects and reports the timing or voltage violations on the interconnect. In this work, we present a test methodology for interconnect testing on SoC systems. Our method employs monitoring cells designed to detect timing and voltage violations on chips. These cells are integrated in several BIST architectures with different test objectives. These efforts may not be pragmatic in testing multi-billion SoCs unless they are able to be automated and efficiently used in SoC system platforms. Therefore, we designed signal integrity test circuitry compliant with IEEE P1500 standard. Our augmentation improves P1500 so it is capable of handling signal integrity in addition to conventional faults.