A hierarchical, automated design flow for low-power, high-throughput digital signal processing IC's

An automated design flow for direct-mapped digital signal processing systems is presented as a possible solution to the design productivity gap. With current semiconductor processing technologies, there is a growing gap between the number of transistors-per-chip that can be fabricated and the transistors-per-day that can be effectively designed. As a result, the only chips that take advantage of current processing capability are programmable processors with large memories or FPGA's, which are very power and area inefficient. Direct-mapped architectures offer the same throughput while using three to four orders of magnitude less energy and area, but they tend to be avoided because of the immense design effort involved. This work presents an automated flow that allows direct-mapped architectures to be designed with much less effort.; The approach of this flow is similar to the silicon compilers of the previous decade, except that it uses commercial CAD tools. A unified, dataflow-graph-based input description captures the essential decisions: function, signal, circuit, and floorplan decisions. An automated flow much like MAKE invokes CAD tools and carries this description through the different design phases to produce mask layout ready for fabrication and estimates of power and speed. Special attention is given to the preservation of hierarchy throughout the flow to help designers see how the different decisions are related and how to fix problems when particular tools break down. The resulting flow differs significantly from commercial CAD flows, because it is comprised of many small jumps from flow, for instance, never creates a complete register-transfer level (RTL) description for each chip.; The flow is demonstrated on three direct-mapped signal-processing chips ranging in complexity from 300,000 to 600,000 transistors, including an iterative decoder for high-speed magnetic read-channels and a complete TDMA baseband receiver for use in low-power sensor networks. These systems are contrasted with a CDMA receiver designed with an industry-standard flow. An effort is made to quantify the complexity and design effort for each of these projects in order to clarify the benefit of this approach.