Test generation for fault isolation in analog and mixed-mode circuits

This dissertation presents a novel set of diagnostic test generation techniques for analog circuits. A complete fault-oriented framework for generating fast transient tests to isolate a faulty component within a malfunctioning analog device is presented. Test generation time and costs are minimized by a novel fault sampling technique that reduces the number of faults in a given fault universe without compromising diagnostic accuracy. A set of complimentary diagnostic test generation algorithms are proposed that generate an optimal set of test stimuli, test measurements and test points to detect and isolate catastrophic and parametric faults in a linear or non-linear analog circuit. The complexity of fault simulation during test optimization is significantly reduced by using hierarchical fault modeling and partial fault simulation techniques. The proposed test generators accommodate measurement inaccuracies and component tolerance effects. Hardware limitations of the testing equipment are considered during test generation to ensure that the diagnostic test can be faithfully reproduced during manufacturing testing. The proposed set of techniques also handle constraints due to limited test access of the device under test. A hierarchical fault dictionary based approach is used for fault diagnosis, and a novel technique is proposed to construct a compact and search-efficient fault dictionary. This significantly reduces manufacturing test and time. Finally, a concurrent fault detection technique is proposed to detect faults in mission-critical systems while in normal operating mode.