Accurate gate delay evaluation of CMOS deep sub-micron VLSI circuits

RC interconnect effects in CMOS deep sub-micron (DSM) VLSI circuits can cause inaccurate timing analysis when classic gate delay modeling approach is used. In this dissertation, an analytical gate delay model is first derived for L-type RC load situation to account for resistance shielding effect. Then using a novel approach, simple and intuitive equations are derived to compute the L-model for a general gate load RC tree. L-model conditions are also resolved in closed-form to assure gate load modeling accuracy. Experiments show that gate delay errors are less than 3.3% if L-model is used under the constraint. Non-liner signal waveform effect is also investigated based on a 0.25micron technology. Results show that a two-ramp signal waveform model that accounts for gate input thresholds is needed to keep gate delay modeling errors within 10%. Finally, in this dissertation, a new empirical gate delay modeling approach is proposed to achieve accurate and efficient gate delay evaluation in challenging DSM circuits. Path delay calculation results using this approach show less than 3.4% errors.